AT89C51IC2-RLRUL Atmel, AT89C51IC2-RLRUL Datasheet - Page 21

• Manufacturer Part Number: AT89C51IC2-RLRUL
• Description: IC 8051 MCU 32K FLASH 44-VQFP
• Manufacturer: Atmel
• Series: 89Cr

Specifications of AT89C51IC2-RLRUL

• Core Processor: 8051
• Core Size: 8-Bit
• Speed: 40MHz
• Connectivity: I²C, SPI, UART/USART
• Peripherals: POR, PWM, WDT
• Number Of I /o: 34
• Program Memory Size: 32KB (32K x 8)
• Program Memory Type: FLASH
• Ram Size: 1.25K x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 3.6 V
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 44-TQFP, 44-VQFP
• Processor Series: AT89x
• Core: 8051
• Data Bus Width: 8 bit
• Data Ram Size: 1280 B
• Interface Type: UART, SPI, TWI
• Maximum Clock Frequency: 60 MHz
• Number Of Programmable I/os: 34
• Number Of Timers: 3
• Operating Supply Voltage: 2.7 V to 5.5 V
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: PK51, CA51, A51, ULINK2
• For Use With: AT89OCD-01 - USB EMULATOR FOR AT8XC51 MCU
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Data Converters: -
• Lead Free Status / Rohs Status: Details
• Other names: AT89C51IC2-RLRULTR

Enhanced Features
X2 Feature and OSCA
Clock Generation
Description
Figure 5. Clock Generation Diagram
4301D–8051–02/08
XTALA1
F
XTAL
In comparison to the original 80C52, the AT89C51IC2 implements some new features,
which are
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The AT89C51IC2 core needs only 6 clock periods per machine cycle. This feature
called ”X2” provides the following advantages:
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In order to keep the original C51 compatibility, a divider by 2 is inserted between the
XTALA1 signal and the main clock input of the core (phase generator). This divider may
be disabled by software.
The clock for the whole circuit and peripherals is first divided by two before being used
by the CPU core and the peripherals.
This allows any cyclic ratio to be accepted on XTALA1 input. In X2 mode, as this divider
is bypassed, the signals on XTALA1 must have a cyclic ratio between 40 to 60%.
Figure 5. shows the clock generation block diagram.x2 bit is validated on the rising edge
of the XTALA1÷2 to avoid glitches when switching from X2 to STD mode. Figure 6.
shows the switching mode waveforms.
2
The X2 option
The Dual Data Pointer
The extended RAM
The Programmable Counter Array (PCA)
The Hardware Watchdog
The SPI interface
The 2-wire interface
The 4 level interrupt priority system
The power-off flag
The Power On Reset
The ONCE mode
The ALE disabling
Some enhanced features are also located in the UART and the timer 2
Divide frequency crystals by 2 (cheaper crystals) while keeping same CPU power.
Save power consumption while keeping same CPU power (oscillator power saving).
Save power consumption by dividing dynamically the operating frequency by 2 in
operating and idle modes.
Increase CPU power by 2 while keeping same crystal frequency.
XTALA1:2
:
CKCON0
X2
0
1
F
OSCA
8 bit Prescaler
CKRL
F
OSCB
CKSEL
CKS
0
1
F
F
CLK CPU
CLK PERIPH
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