AT89C51IC2-RLRUL Atmel, AT89C51IC2-RLRUL Datasheet - Page 68

IC 8051 MCU 32K FLASH 44-VQFP

AT89C51IC2-RLRUL

Manufacturer Part Number
AT89C51IC2-RLRUL
Description
IC 8051 MCU 32K FLASH 44-VQFP
Manufacturer
Atmel
Series
89Cr
Datasheet

Specifications of AT89C51IC2-RLRUL

Core Processor
8051
Core Size
8-Bit
Speed
40MHz
Connectivity
I²C, SPI, UART/USART
Peripherals
POR, PWM, WDT
Number Of I /o
34
Program Memory Size
32KB (32K x 8)
Program Memory Type
FLASH
Ram Size
1.25K x 8
Voltage - Supply (vcc/vdd)
2.7 V ~ 3.6 V
Oscillator Type
External
Operating Temperature
-40°C ~ 85°C
Package / Case
44-TQFP, 44-VQFP
Processor Series
AT89x
Core
8051
Data Bus Width
8 bit
Data Ram Size
1280 B
Interface Type
UART, SPI, TWI
Maximum Clock Frequency
60 MHz
Number Of Programmable I/os
34
Number Of Timers
3
Operating Supply Voltage
2.7 V to 5.5 V
Mounting Style
SMD/SMT
3rd Party Development Tools
PK51, CA51, A51, ULINK2
For Use With
AT89OCD-01 - USB EMULATOR FOR AT8XC51 MCU
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Data Converters
-
Lead Free Status / Rohs Status
 Details
Other names
AT89C51IC2-RLRULTR

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
AT89C51IC2-RLRUL
Manufacturer:
Atmel
Quantity:
10 000
Warm Reset
Watchdog Reset
68
AT89C51IC2
Table 1. Minimum Reset Capacitor Value for a 50 kΩ Pull-down Resistor
Note:
To achieve a valid reset, the reset signal must be maintained for at least 2 machine
cycles (24 oscillator clock periods) while the oscillator is running. The number of clock
periods is mode independent (X2 or X1).
As detailed in Section “Hardware Watchdog Timer”, page 102, the WDT generates a 96-
clock period pulse on the RST pin. In order to properly propagate this pulse to the rest of
the application in case of external capacitor or power-supply supervisor circuit, a 1 kΩ
resistor must be added as shown Figure 24.
Figure 24. Reset Circuitry for WDT Reset-out Usage
Start-Up Time
Oscillator
20 ms
These values assume V
on/off sequences is too fast, the power-supply de-coupling capacitors may not be fully
discharged, leading to a bad reset sequence.
5 ms
VDD
VDD
VSS
+
RST
1K
820 nF
2.7 µF
1 ms
DD
RST
starts from 0V to the nominal value. If the time between 2
VSS
VDD
P
VDD Rise Time
1.2 µF
3.9 µF
10 ms
From WDT
Reset Source
To CPU Core
and Peripherals
To Other
On-board
Circuitry
100 ms
(1)
4301D–8051–02/08
12 µF
12 µF

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