M30879FKBGP#U5 Renesas Electronics America, M30879FKBGP#U5 Datasheet - Page 245

• Manufacturer Part Number: M30879FKBGP#U5
• Description: IC M32C/87 MCU FLASH 100LQFP
• Manufacturer: Renesas Electronics America
• Series: M16C™ M32C/80r

Specifications of M30879FKBGP#U5

• Core Processor: M32C/80
• Core Size: 16/32-Bit
• Speed: 32MHz
• Connectivity: EBI/EMI, I²C, IEBus, IrDA, SIO, UART/USART
• Peripherals: DMA, POR, PWM, WDT
• Number Of I /o: 85
• Program Memory Size: 768KB (768K x 8)
• Program Memory Type: FLASH
• Ram Size: 48K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 5.5 V
• Data Converters: A/D 26x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 85°C
• Package / Case: 100-LQFP
• For Use With: R0K330879S001BE - KIT DEV RSK M32C/87R0K330879S000BE - KIT DEV RSK M32C/87
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

M32C/87 Group (M32C/87, M32C/87A, M32C/87B)
REJ09B0180-0151 Rev.1.51 Jul 31, 2008
Page 221 of 587
Figure 17.7
UARTi Transmit/Receive Control Register 0 (i = 0 to 4)
b7 b6 b5 b4
NOTES:
1. Set the UiBRG register after setting bits CLK1 and CLK0.
2. Bits CNT3 to CNT0 in the TCSPR register select no division (n = 0) or divide-by-2n (n = 1 to 15). To select f2n, set the
3. P7_0/TXD2, P7_1/SCL2 are N-channel open drain output ports. They cannot be set as CMOS output ports even if the NCH bit
4. The UFORM bit is enabled when bits SMD2 to SMD0 in the UiMR register are set to 001b (clock synchronous mode) or 101b
CST bit in the TCSPR register to 1 before setting bits CLK1 and CLK0 to 10b.
is set to 0.
(UART mode, 8-bit data length). Set the UFORM bit to 1 when bits SMD2 to SMD0 are set to 010b (I
SMD2 to SMD0 are set to 100b (UART mode, 7-bit data length) or 110b (UART mode, 9-bit data length).
b3
b2
U0C0 to U4C0 Registers
b1
b0
Bit Symbol
UFORM
CKPOL
TXEPT
CLK0
CLK1
CRD
NCH
CRS
Symbol
U0C0 to U2C0
U3C0, U4C0
UiBRG count source select
bits
CTS function select bit
Transmit shift register
empty flag
CTS function disable bit
Data output select bit
CLK polarity select bit
Bit order select bit
(1)
Bit Name
(4)
3)
Address
036Ch, 02ECh, 033Ch
032Ch, 02FCh
0: TXDi/SDAi and SCLi are CMOS output ports
1: TXDi/SDAi and SCLi are N-channel open
b1 b0
0 0: f1 selected
0 1: f8 selected
1 0: f2n selected
1 1: Do not set to this value
Enabled when CRD = 0
0: CTS function selected
1: CTS function not selected
0: Data in the transmit shift register
1: No data in the transmit shift register
0: CTS function enabled
1: CTS function disabled
0: Transmit data output at the falling edge and
1: Transmit data output at the rising edge and
0 : LSB first
1 : MSB first
drain output ports
receive data input at the rising edge of the
serial clock
receive data input at the falling edge of the
serial clock
(during transmit operation)
(transmit operation is completed)
17. Serial Interfaces (UART0 to UART4)
(2)
Function
2
C mode), or to 0 when bits
After Reset
0000 1000b
0000 1000b
RW
RW
RW
RW
RO
RW
RW
RW
RW