ATTINY88-15MZ Atmel, ATTINY88-15MZ Datasheet - Page 44

• Manufacturer Part Number: ATTINY88-15MZ
• Description: IC MCU AVR 8B 8KB FLASH 32QFN
• Manufacturer: Atmel
• Series: AVR® ATtinyr

Specifications of ATTINY88-15MZ

• Core Processor: AVR
• Core Size: 8-Bit
• Speed: 16MHz
• Connectivity: I²C, SPI
• Peripherals: Brown-out Detect/Reset, POR, WDT
• Number Of I /o: 28
• Program Memory Size: 8KB (4K x 16)
• Program Memory Type: FLASH
• Eeprom Size: 64 x 8
• Ram Size: 512 x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 5.5 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 125°C
• Package / Case: *
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

8.4.1
8.4.2
8.4.3
44
ATtiny88 Automotive
Timed Sequences for Changing the Configuration of the Watchdog Timer
Safety Level 1
Safety Level 2
To prevent unintentional disabling of the Watchdog or unintentional change of time-out period,
two different safety levels are selected by the fuse WDTON as shown in Table 8-1. See
Sequences for Changing the Configuration of the Watchdog Timer” on page 44
Table 8-1.
Figure 8-7.
The sequence for changing configuration differs slightly between the two safety levels. Separate
procedures are described for each level.
In this mode, the Watchdog Timer is initially disabled, but can be enabled by writing the WDE bit
to one without any restriction. A timed sequence is needed when disabling an enabled
Watch-dog Timer. To disable an enabled Watchdog Timer, the following procedure must be
followed:
In this mode, the Watchdog Timer is always enabled, and the WDE bit will always read as one. A
timed sequence is needed when changing the Watchdog Time-out period. To change the
Watchdog Time-out, the following procedure must be followed:
WDTON
Unprogrammed
Programmed
1. In the same operation, write a logic one to WDCE and WDE. A logic one must be writ-
2. Within the next four clock cycles, in the same operation, write the WDE and WDP bits
1. In the same operation, write a logical one to WDCE and WDE. Even though the WDE
2. Within the next four clock cycles, in the same operation, write the WDP bits as desired,
ten to WDE regardless of the previous value of the WDE bit.
as desired, but with the WDCE bit cleared.
always is set, the WDE must be written to one to start the timed sequence.
but with the WDCE bit cleare d. The value written to the WDE bit is irrelevant.
WDT Configuration as a Function of the WDTON Fuse Setting
Watchdog Timer
Safety Level
WATCHDOG
RESET
OSCILLATOR
128kHz
1
2
WDIE
WDIF
WDE
WDT Initial State
Disabled
Enabled
Disable WDT
Timed sequence
Always enabled
WDP0
WDP1
WDP2
WDP3
MCU RESET
INTERRUPT
Change Time-out
No limitations
Timed sequence
for details.
9157B–AVR–01/10
“Timed