PIC16LC433-I/P Microchip Technology, PIC16LC433-I/P Datasheet - Page 60

• Manufacturer Part Number: PIC16LC433-I/P
• Description: IC MCU CMOS 8BIT 10MHZ 2K 18-DIP
• Manufacturer: Microchip Technology
• Series: PIC® 16Cr

Specifications of PIC16LC433-I/P

• Core Processor: PIC
• Core Size: 8-Bit
• Speed: 10MHz
• Connectivity: LIN (Local Interconnect Network)
• Peripherals: POR, WDT
• Number Of I /o: 6
• Program Memory Size: 3.5KB (2K x 14)
• Program Memory Type: OTP
• Ram Size: 128 x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 5.5 V
• Data Converters: A/D 4x8b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 18-DIP (0.300", 7.62mm)
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

PIC16C433
9.5
There are four sources of interrupt:
The Interrupt Control Register (INTCON) records indi-
vidual interrupt requests in flag bits. It also has individ-
ual and global interrupt enable bits.
A global interrupt enable bit, GIE (INTCON<7>),
enables (if set) all unmasked interrupts, or disables (if
cleared) all interrupts. When bit GIE is enabled and an
interrupt’s flag bit and mask bit are set, the interrupt will
vector immediately. Individual interrupts can be dis-
abled through their corresponding enable bits in vari-
ous registers. Individual interrupt flag bits are set,
regardless of the status of their corresponding mask bit
or the GIE bit. The GIE bit is cleared on RESET.
FIGURE 9-14: INTERRUPT LOGIC
DS41139A-page 58
TMR0 Overflow Interrupt
External Interrupt GP2/INT pin
GPIO Port Change Interrupts (pins GP0, GP1, GP3)
A/D Interrupt
Note:
Interrupts
Individual interrupt flag bits are set, regard-
less of the status of their corresponding
mask bit, or the GIE bit.
Interrupt Sources
ADIF
ADIE
INTF
INTE
T0IF
T0IE
GPIF
GPIE
PEIE
GIE
Advance Information
The “return-from-interrupt” instruction, RETFIE, exits
the interrupt routine, as well as sets the GIE bit, which
re-enables interrupts.
The GP2/INT, GPIO port change interrupt and the
TMR0 overflow interrupt flags are contained in the
INTCON register.
The peripheral interrupt flag ADIF, is contained in the
Special Function Register PIR1. The corresponding
interrupt enable bit is contained in Special Function
Register PIE1, and the peripheral interrupt enable bit is
contained in Special Function Register INTCON.
When an interrupt is responded to, the GIE bit is
cleared to disable any further interrupt, the return
address is pushed onto the stack and the PC is loaded
with 0004h. Once in the Interrupt Service Routine, the
source(s) of the interrupt can be determined by polling
the interrupt flag bits. The interrupt flag bit(s) must be
cleared in software before re-enabling interrupts to
avoid repeated interrupts.
For external interrupt events, such as GPIO change
interrupt, the interrupt latency will be three or four
instruction cycles. The exact latency depends on when
the interrupt event occurs (Figure 9-15). The latency is
the same for one or two cycle instructions. Individual
interrupt flag bits are set, regardless of the status of
their corresponding mask bit or the GIE bit.
Wake-up
(If in SLEEP mode)
Interrupt to CPU
2001 Microchip Technology Inc.