PIC16C433-E/SO Microchip Technology, PIC16C433-E/SO Datasheet - Page 39

• Manufacturer Part Number: PIC16C433-E/SO
• Description: IC MCU CMOS 8BIT 10MHZ 2K 18SOIC
• Manufacturer: Microchip Technology
• Series: PIC® 16Cr

Specifications of PIC16C433-E/SO

• Core Processor: PIC
• Core Size: 8-Bit
• Speed: 10MHz
• Connectivity: LIN (Local Interconnect Network)
• Peripherals: POR, WDT
• Number Of I /o: 5
• Program Memory Size: 3.5KB (2K x 14)
• Program Memory Type: OTP
• Ram Size: 128 x 8
• Voltage - Supply (vcc/vdd): 4.5 V ~ 5.5 V
• Data Converters: A/D 4x8b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 125°C
• Package / Case: 18-SOIC (7.5mm Width)
• For Use With: AC164030 - MODULE SKT PROMATEII 28DIP/SOIC
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

7.0
The Timer0 module timer/counter has the following
features:
• 8-bit timer/counter
• Readable and writable
• 8-bit software programmable prescaler
• Internal or external clock select
• Interrupt on overflow from FFh to 00h
• Edge select for external clock
Figure 7-1 is a simplified block diagram of the Timer0
module.
Timer mode is selected by clearing bit T0CS
(OPTION<5>). In Timer mode, the Timer0 module will
increment every instruction cycle (without prescaler). If
the TMR0 register is written, the increment is inhibited
for the following two instruction cycles (Figure 7-2 and
Figure 7-3). The user can work around this by writing
an adjusted value to the TMR0 register.
Counter mode is selected by setting bit T0CS
(OPTION<5>). In Counter mode, Timer0 will increment
either on every rising or falling edge of pin RA4/T0CKI.
The incrementing edge is determined by the bit T0SE
FIGURE 7-1:
FIGURE 7-2:
 2002 Microchip Technology Inc.
GP2/TOCKI/
AN2/INT
PC
(Program
Counter)
Instruction
Fetch
TMR0
Instruction
Executed
Note 1:
TIMER0 MODULE
2:
TOCS, TOSE, PSA, PS<2:0> (OPTION<5:0>).
The prescaler is shared with Watchdog Timer (refer to Figure 7-6 for detailed block diagram).
TOSE
Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4
T0
TIMER0 BLOCK DIAGRAM
TIMER0 TIMING: INTERNAL CLOCK/NO PRESCALE
F
OSC
PC-1
/4
MOVWF TMR0 MOVF TMR0,W MOVF TMR0,W MOVF TMR0,W MOVF TMR0,W MOVF TMR0,W
T0+1
TOCS
PC
0
1
T0+2
Write TMR0
executed
Programmable
PC+1
PS<2:0>
Prescaler
3
Preliminary
NT0
Read TMR0
reads NT0
PC+2
PSA
1
0
(OPTION<4>). Clearing bit T0SE selects the rising
edge. Restrictions on the external clock input are dis-
cussed in detail in Section 7.2.
The prescaler is mutually exclusively shared between
the Timer0 module and the Watchdog Timer. The
prescaler assignment is controlled in software by con-
trol bit PSA (OPTION<3>). Clearing bit PSA will assign
the prescaler to the Timer0 module. The prescaler is
not readable or writable. When the prescaler is
assigned to the Timer0 module, pre-scale values of 1:2,
1:4, ..., 1:256 are selectable. Section 7.3 details the
operation of the prescaler.
7.1
The TMR0 interrupt is generated when the TMR0 reg-
ister overflows from FFh to 00h. This overflow sets bit
T0IF (INTCON<2>). The interrupt can be masked by
clearing bit T0IE (INTCON<5>). Bit T0IF must be
cleared in software by the Timer0 module Interrupt Ser-
vice Routine before re-enabling this interrupt. The
TMR0 interrupt cannot awaken the processor from
SLEEP, since the timer is shut-off during SLEEP. See
Figure 7-4 for Timer0 interrupt timing.
Read TMR0
reads NT0
NT0
PC+3
(2 T
Timer0 Interrupt
Sync with
Internal
Clocks
CY
delay)
Read TMR0
reads NT0
NT0
PC+4
PIC16C433
Read TMR0
reads NT0 + 1
NT0+1
Data Bus
TMR0
PC+5
8
DS41139B-page 37
Read TMR0
reads NT0 + 2
Flag bit T0IF
Set Interrupt
on Overflow
NT0+2
PC+6
T0