IC 8051 MCU FLASH 32K 44PLCC

AT89C51RC-24JU

Manufacturer Part NumberAT89C51RC-24JU
DescriptionIC 8051 MCU FLASH 32K 44PLCC
ManufacturerAtmel
Series89C
AT89C51RC-24JU datasheet
 

Specifications of AT89C51RC-24JU

Core Processor8051Core Size8-Bit
Speed24MHzConnectivitySPI, UART/USART
PeripheralsWDTNumber Of I /o32
Program Memory Size32KB (32K x 8)Program Memory TypeFLASH
Ram Size512 x 8Voltage - Supply (vcc/vdd)4 V ~ 5.5 V
Oscillator TypeInternalOperating Temperature-40°C ~ 85°C
Package / Case44-PLCCPackage44PLCC
Device Core8051Family Name89C
Maximum Speed24 MHzOperating Supply Voltage5 V
Data Bus Width8 BitNumber Of Programmable I/os32
Interface TypeUARTNumber Of Timers3
Processor SeriesAT89xCore8051
Data Ram Size512 BMaximum Clock Frequency33 MHz
Maximum Operating Temperature+ 85 CMounting StyleSMD/SMT
3rd Party Development ToolsPK51, CA51, A51, ULINK2Minimum Operating Temperature- 40 C
For Use WithAT89STK-11 - KIT STARTER FOR AT89C51RX2Lead Free Status / RoHS StatusLead free / RoHS Compliant
Eeprom Size-Data Converters-
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Features
®
Compatible with MCS
-51 Products
32K Bytes of Reprogrammable Flash Memory
Endurance: 10,000 Write/Erase Cycles
4V to 5.5V Operating Range
Fully Static Operation: 0 Hz to 33 MHz
Three-level Program Memory Lock
512 x 8-bit Internal RAM
32 Programmable I/O Lines
Three 16-bit Timer/Counters
Eight Interrupt Sources
Programmable Serial Channel
Low-power Idle and Power-down Modes
Interrupt Recovery from Power-down Mode
Hardware Watchdog Timer
Dual Data Pointer
Power-off Flag
Green (Pb/Halide-free) Packaging Option
1. Description
The AT89C51RC is a low-power, high-performance CMOS 8-bit microcontroller with
32K bytes of Flash programmable read-only memory and 512 bytes of RAM. The
device is manufactured using Atmel’s high-density nonvolatile memory technology
and is compatible with the industry-standard 80C51 and 80C52 instruction set and
pinout. The on-chip Flash allows the program memory to be user programmed by a
conventional nonvolatile memory programmer. A total of 512 bytes of internal RAM
are available in the AT89C51RC. The 256-byte expanded internal RAM is accessed
via MOVX instructions after clearing bit 1 in the SFR located at address 8EH. The
other 256-byte RAM segment is accessed the same way as the Atmel AT89-series
and other 8052-compatible products. By combining a versatile 8-bit CPU with Flash
on a monolithic chip, the Atmel AT89C51RC is a powerful microcomputer which pro-
vides a highly-flexible and cost-effective solution to many embedded control
applications.
The AT89C51RC provides the following standard features: 32K bytes of Flash, 512
bytes of RAM, 32 I/O lines, three 16-bit timer/counters, a six-vector two-level interrupt
architecture, a full duplex serial port, on-chip oscillator, and clock circuitry. In addition,
the AT89C51RC is designed with static logic for operation down to zero frequency
and supports two software selectable power saving modes. The Idle Mode stops the
CPU while allowing the RAM, timer/counters, serial port, and interrupt system to con-
tinue functioning. The Power-down mode saves the RAM contents but freezes the
oscillator, disabling all other chip functions until the next external interrupt or hardware
reset.
8-bit
Microcontroller
with 32K Bytes
Flash
AT89C51RC
1920D–MICRO–6/08

AT89C51RC-24JU Summary of contents

  • Page 1

    ... RAM, 32 I/O lines, three 16-bit timer/counters, a six-vector two-level interrupt architecture, a full duplex serial port, on-chip oscillator, and clock circuitry. In addition, the AT89C51RC is designed with static logic for operation down to zero frequency and supports two software selectable power saving modes. The Idle Mode stops the CPU while allowing the RAM, timer/counters, serial port, and interrupt system to con- tinue functioning ...

  • Page 2

    ... Pin Configurations 2.1 44A – 44-lead TQFP 2.2 44J – 44-lead PLCC 2.3 40P6 – 40-lead PDIP AT89C51RC RST 4 30 (RXD) P3 (TXD) P3 (INT0) P3 (INT1) P3 (T0) P3.4 10 (T1 P0.4 (AD4) P1 P0.5 (AD5) P1 P0.6 (AD6) RST 10 36 P0.7 (AD7) (RXD) P3.0 ...

  • Page 3

    ... RAM LATCH ACC TMP1 TMP2 ALU INTERRUPT, SERIAL PORT, AND TIMER BLOCKS PSW INSTRUCTION REGISTER PORT 1 LATCH WATCH DOG PORT 1 DRIVERS P1.0 - P1.7 AT89C51RC P2.0 - P2.7 PORT 2 DRIVERS PORT 2 FLASH LATCH PROGRAM STACK ADDRESS POINTER REGISTER BUFFER PC INCREMENTER PROGRAM COUNTER DUAL ...

  • Page 4

    ... Port 2 uses strong internal pull-ups when emitting 1s. During accesses to external data memory that use 8-bit addresses (MOVX @ RI), Port 2 emits the contents of the P2 Special Function Register. Port 2 also receives the high-order address bits and some control signals during Flash program- ming and verification. AT89C51RC 4 ) because of the internal pull-ups. IL Alternate Functions ...

  • Page 5

    ... As inputs, Port 3 pins that are externally being pulled low will source current (I Port 3 receives some control signals for Flash programming and verification. Port 3 also serves the functions of various special features of the AT89C51RC, as shown in the following table. Port Pin P3 ...

  • Page 6

    ... Input to the inverting oscillator amplifier and input to the internal clock operating circuit. 4.12 XTAL2 Output from the inverting oscillator amplifier. 5. Special Function Registers A map of the on-chip memory area called the Special Function Register (SFR) space is shown in Table 5-1. AT89C51RC SFR Map and Reset Values 0F8H B 0F0H 00000000 0E8H ACC ...

  • Page 7

    ... Power Off Flag: The Power Off Flag (POF) is located at bit 4 (PCON.4) in the PCON SFR. POF is set to “1” during power up. It can be set and reset under software control and is not affected by reset. 1920D–MICRO–6/08 Table 13-1 and Table 5-4) for Timer 2. The register pair (RCAP2H, AT89C51RC Table 5- 7 ...

  • Page 8

    ... Capture/Reload select. CP/RL2 = 1 causes captures to occur on negative transitions at T2EX if EXEN2 = 1. CP/RL2 = 0 CP/RL2 causes automatic reloads to occur when Timer 2 overflows or negative transitions occur at T2EX when EXEN2 = 1. When either RCLK or TCLK = 1, this bit is ignored and the timer is forced to auto-reload on Timer 2 overflow. AT89C51RC 8 RCLK TCLK ...

  • Page 9

    ... Reserved for future expansion DPS Data Pointer Register Select DPS 0 Selects DPTR Registers DP0L, DP0H 1 Selects DPTR Registers DP1L, DP1H 1920D–MICRO–6/08 – – WDIDLE DISRTO – – – – AT89C51RC Reset Value = XXX00X00B – EXTRAM DISALE Reset Value = XXXXXXX0B – – DPS ...

  • Page 10

    ... Data Memory The AT89C51RC has internal data memory that is mapped into four separate segments: the lower 128 bytes of RAM, upper 128 bytes of RAM, 128 bytes special function register (SFR) and 256 bytes expanded RAM (ERAM). The four segments are: 1 ...

  • Page 11

    ... RESET HIGH pulse at the RST pin. 1920D–MICRO–6/08 Internal and External Data Memory Address (with EXTRAM = UPPER 128 BYTES INTERNAL RAM ERAM 80 256 BYTES LOWER 128 BYTES INTERNAL RAM 00 00 AT89C51RC FFFF SPECIAL EXTERNAL FUNCTION DATA REGISTER MEMORY 80 0100 0000 Figure 11 ...

  • Page 12

    ... With WDIDLE bit enabled, the WDT will stop to count in IDLE mode and resumes the count upon exit from IDLE. 11. UART The UART in the AT89C51RC operates the same way as the UART in the AT89C51 and AT89C52. For more detailed information on the UART operation, please click on the document link below: http://www ...

  • Page 13

    ... Timer 0 and 1 Timer 0 and Timer 1 in the AT89C51RC operate the same way as Timer 0 and Timer 1 in the AT89C51 and AT89C52. For further information on the timers’ operation, please click on the document link below: http://www.atmel.com/dyn/resources/prod_documents/DOC4316.PDF 13. Timer 2 Timer 16-bit Timer/Counter that can operate as either a timer or an event counter. The type of operation is selected by bit C/T2 in the SFR T2CON (shown in three operating modes: capture, auto-reload (up or down counting), and baud rate generator ...

  • Page 14

    ... In this operating mode, EXF2 does not flag an interrupt. Figure 13-1. Timer in Capture Mode ÷12 OSC T2 PIN TRANSITION DETECTOR T2EX PIN AT89C51RC 14 Table 13-2). Upon reset, the DCEN bit is set that timer 2 will default to shows Timer 2 automatically counting up when DCEN=0. In this mode, two options C/ TH2 CONTROL ...

  • Page 15

    ... EXEN2 – – – (DOWN COUNTING RELOAD VALUE) 0FFH 0FFH OVERFLOW C/ TH2 TL2 CONTROL TR2 C/ RCAP2H RCAP2L (UP COUNTING RELOAD VALUE) AT89C51RC TL2 OVERFLOW TIMER 2 INTERRUPT RCAP2L TF2 EXF2 Reset Value = XXXX XX00B – T2OE DCEN TOGGLE EXF2 TF2 TIMER 2 INTERRUPT COUNT ...

  • Page 16

    ... RCAP2L) is the content of RCAP2H and RCAP2L taken as a 16-bit unsigned integer. Timer baud rate generator is shown in TCLK = 1 in T2CON. Note that a rollover in TH2 does not set TF2 and will not generate an inter- AT89C51RC 16 Mdes 1 and 3 Baud Rates NOTE: OSC. FREQ. IS DIVIDED BY 2, NOT 12 ÷ ...

  • Page 17

    ... Figure 15-1. Timer 2 in Clock-Out Mode P1.0 (T2) P1.1 (T2EX) 1920D–MICRO–6/08 Clock-Out Frequency = ------------------------------------------------------------------------------------ - 4 x [65536-(RCAP2H,RCAP2L)] ÷2 OSC TRANSITION DETECTOR EXEN2 AT89C51RC Figure Oscillator Frequency TL2 TH2 (8-BITS) (8-BITS) TR2 RCAP2L RCAP2H C/T2 BIT ÷2 T2OE (T2MOD.1) TIMER 2 EXF2 INTERRUPT 15-1 ...

  • Page 18

    ... Interrupts The AT89C51RC has a total of six interrupt vectors: two external interrupts (INT0 and INT1), three timer interrupts (Timers 0, 1, and 2), and the serial port interrupt. These interrupts are all shown in Each of these interrupt sources can be individually enabled or disabled by setting or clearing a bit in Special Function Register IE. IE also contains a global disable bit, EA, which disables all interrupts at once ...

  • Page 19

    ... INT0 1 TF0 0 INT1 1 TF1 TI RI TF2 EXF2 Figure AT89C51RC IE0 IE1 19-1. Either a quartz crystal or Figure 19-2. There are no 19 ...

  • Page 20

    ... Figure 19-1. Oscillator Connections Note: Figure 19-2. External Clock Drive Configuration Table 19-1. Mode Idle Idle Power-down Power-down AT89C51RC C1 ± for Crystals = 40 pF ± for Ceramic Resonators NC EXTERNAL OSCILLATOR SIGNAL Status of External Pins During Idle and Power-down Modes ...

  • Page 21

    ... Program Memory Lock Bits The AT89C51RC has three lock bits that can be left unprogrammed (U) or can be programmed (P) to obtain the additional features listed in Table 20- When lock bit 1 is programmed, the logic level at the EA pin is sampled and latched during reset. If the device is powered up without a reset, the latch initializes to a random value and holds that value until reset is activated ...

  • Page 22

    ... Pulse ALE/PROG once (duration of 200 ns - 500 ns) and wait for 150 ms. 5. Power V Data Polling: The AT89C51RC features Data Polling to indicate the end of a write cycle. During a write cycle, an attempted read of the last byte written will result in the complement of the writ- ten data on P0.7. Once the write cycle has been completed, true data is valid on all outputs, and the next cycle may begin ...

  • Page 23

    ... Write Lock Bits requires a 100 µs PROG pulse. 3. Chip Erase requires a 200 ns - 500 ns PROG pulse. 4. RDY/BSY signal is output on P3.0 during programming. 1920D–MICRO–6/08 ALE/ EA/ PROG V P2.6 P2 (3) L 12V AT89C51RC P3.4 P0.7-0 P3.3 P3.6 P3.7 Data A14 A14 OUT P0. P0. 1EH 51H 07H X P2.5-0 P1 ...

  • Page 24

    ... P0 DATA P3.4 P2.6 P2.7 ALE PROG P3.3 P3.6 P3.7 XTAL2 RDY/ P3.0 BSY XTAL1 RST V IH GND PSEN 4.5V to 5.5V AT89C51RC V P1.0 - P1.7 CC PGM DATA P0 P2.0 - P2.5 (USE 10K P3.4 PULL-UPS) P2.6 P2.7 ALE P3.3 P3 P3.7 XTAL XTAL1 RST IH GND PSEN ...

  • Page 25

    ... GLGH t Address to Data Valid AVQV t ENABLE Low to Data Valid ELQV t Data Float after ENABLE EHQZ t PROG High to BUSY Low GHBL t Byte Write Cycle Time WC 1920D–MICRO–6/08 PP AT89C51RC Min Max Units 11.5 12 MHz 48t CLCL 48t CLCL 48t CLCL 48t CLCL ...

  • Page 26

    ... P3.0 (RDY/BSY) 25. Lock Bit Programming Test Conditions Setup Lockbit_1 Data Setup ALE/PROG V = 6.5V CC 26. Parallel Chip Erase Mode Test Conditions Setup 200 ns ALE/PROG P3<0> Erase V = 6.5V CC AT89C51RC 26 PROGRAMMING ADDRESS DATA DVGL GHDX t t AVGL GHAX t t SHGL GHSL t GLGH EHSH ...

  • Page 27

    ... OL may exceed the related specification. Pins are not guaranteed to sink current greater OL AT89C51RC Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent dam- age to the device. This is a stress rating only and functional operation of the device at these or any ...

  • Page 28

    ... Address Low AVWL t Data Valid to WR Transition QVWX t Data Valid to WR High QVWH t Data Hold after WR WHQX t RD Low to Address Float RLAZ High to ALE High WHLH AT89C51RC 28 12 MHz Oscillator Variable Oscillator Min Max Min 0 127 2t -40 CLCL 43 t -25 CLCL 48 t -25 ...

  • Page 29

    ... AVLL LLIV t LLPL t PLIV t PLAZ t LLAX INSTR IN t AVIV A8 - A15 t LHLL t LLDV t RLRH t LLWL t LLAX t RLDV t AVLL t RLAZ DATA IN t AVWL t AVDV P2 A15 FROM DPH AT89C51RC t PLPH t PXAV t PXIZ PXIX A15 t WHLH t RHDZ t RHDX FROM PCL INSTR A15 FROM PCH 29 ...

  • Page 30

    ... External Clock Drive Symbol Parameter 1/t Oscillator Frequency CLCL t Clock Period CLCL t High Time CHCX t Low Time CLCX t Rise Time CLCH t Fall Time CHCL AT89C51RC 30 t LHLL t t LLWL WLWH t LLAX t t QVWX AVLL t QVWH DATA OUT t AVWL P2 A15 FROM DPH t ...

  • Page 31

    ... V LOAD Points - 0.1V V LOAD 1. For timing purposes, a port pin is no longer floating when a 100 mV change from load voltage occurs. A port pin begins to float when a 100 mV change from the loaded V occurs. AT89C51RC Variable Oscillator Max Min Max 12t CLCL 10t - 133 CLCL ...

  • Page 32

    ... Ordering Information 39.1 Green Package Option (Pb/Halide-free) Speed Power (MHz) Supply Ordering Code AT89C51RC-24AU 24 4.0V to 5.5V AT89C51RC-24JU AT89C51RC-24PU AT89C51RC-33AU 33 4.5V to 5.5V AT89C51RC-33JU AT89C51RC-33PU 44A 44-lead, Thin Plastic Gull Wing Quad Flatpack (TQFP) 44J 44-lead, Plastic J-leaded Chip Carrier (PLCC) 40P6 40-lead, 0.600" Wide, Plastic Dual Inline Package (PDIP) ...

  • Page 33

    ... Orchard Parkway San Jose, CA 95131 R 1920D–MICRO–6/08 B PIN 1 IDENTIFIER TITLE 44A, 44-lead Body Size, 1.0 mm Body Thickness, 0.8 mm Lead Pitch, Thin Profile Plastic Quad Flat Package (TQFP) AT89C51RC A2 A COMMON DIMENSIONS (Unit of Measure = mm) MIN NOM SYMBOL A – – A1 0.05 – ...

  • Page 34

    ... Allowable protrusion is .010"(0.254 mm) per side. Dimension D1 and E1 include mold mismatch and are measured at the extreme material condition at the upper or lower parting line. 3. Lead coplanarity is 0.004" (0.102 mm) maximum. 2325 Orchard Parkway San Jose, CA 95131 R AT89C51RC 34 1.14(0.045) X 45˚ PIN NO. 1 IDENTIFIER E1 E ...

  • Page 35

    ... Mold Flash or Protrusion shall not exceed 0.25 mm (0.010"). 2325 Orchard Parkway San Jose, CA 95131 R 1920D–MICRO–6/08 D PIN 0º ~ 15º REF eB TITLE 40P6, 40-lead (0.600"/15.24 mm Wide) Plastic Dual Inline Package (PDIP) AT89C51RC E1 A1 COMMON DIMENSIONS (Unit of Measure = mm) MIN SYMBOL NOM A – – A1 0.381 – D 52.070 – ...

  • Page 36

    ... Disclaimer: The information in this document is provided in connection with Atmel products. No license, express or implied, by estoppel or otherwise, to any intellectual property right is granted by this document or in connection with the sale of Atmel products. EXCEPT AS SET FORTH IN ATMEL’S TERMS AND CONDI- TIONS OF SALE LOCATED ON ATMEL’S WEB SITE, ATMEL ASSUMES NO LIABILITY WHATSOEVER AND DISCLAIMS ANY EXPRESS, IMPLIED OR STATUTORY WARRANTY RELATING TO ITS PRODUCTS INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTY OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, OR NON-INFRINGEMENT ...