DSPIC30F3013T-20I/ML Microchip Technology, DSPIC30F3013T-20I/ML Datasheet - Page 13

• Manufacturer Part Number: DSPIC30F3013T-20I/ML
• Description: IC DSPIC MCU/DSP 24K 44QFN
• Manufacturer: Microchip Technology
• Series: dsPIC™ 30Fr

Specifications of DSPIC30F3013T-20I/ML

• Core Processor: dsPIC
• Core Size: 16-Bit
• Speed: 20 MIPS
• Connectivity: I²C, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, POR, PWM, WDT
• Number Of I /o: 20
• Program Memory Size: 24KB (8K x 24)
• Program Memory Type: FLASH
• Eeprom Size: 1K x 8
• Ram Size: 2K x 8
• Voltage - Supply (vcc/vdd): 2.5 V ~ 5.5 V
• Data Converters: A/D 10x12b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 44-QFN
• For Use With: DV164033 - KIT START EXPLORER 16 MPLAB ICD2DM240001 - BOARD DEMO PIC24/DSPIC33/PIC32
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

TABLE 5-7:
© 2010 Microchip Technology Inc.
FWPSA<1:0> FWDT
FWPSB<3:0> FWDT
FWDTEN
MCLREN
PWMPIN
HPOL
LPOL
BOREN
BORV<1:0>
FPWRT<1:0> FBORPOR
RBS<1:0>
Bit Field
FWDT
FBORPOR
FBORPOR
FBORPOR
FBORPOR
FBORPOR
FBORPOR
FBS
CONFIGURATION BITS DESCRIPTION
Register
Watchdog Timer Prescaler A
11 = 1:512
10 = 1:64
01 = 1:8
00 = 1:1
Watchdog Timer Prescaler B
1111 = 1:16
1110 = 1:15
0001 = 1:2
0000 = 1:1
Watchdog Enable
1 = Watchdog enabled (LPRC oscillator cannot be disabled. Clearing the SWDTEN
0 = Watchdog disabled (LPRC oscillator can be disabled by clearing the SWDTEN bit
Master Clear Enable
1 = Master Clear pin (MCLR) is enabled
0 = MCLR pin is disabled
Motor Control PWM Module Pin Mode
1 = PWM module pins controlled by PORT register at device Reset (tri-stated)
0 = PWM module pins controlled by PWM module at device Reset (configured as out-
Motor Control PWM Module High-Side Polarity
1 = PWM module high-side output pins have active-high output polarity
0 = PWM module high-side output pins have active-low output polarity
Motor Control PWM Module Low-Side Polarity
1 = PWM module low-side output pins have active-high output polarity
0 = PWM module low-side output pins have active-low output polarity
PBOR Enable
1 = PBOR enabled
0 = PBOR disabled
Brown-out Voltage Select
11 = 2.0V (not a valid operating selection)
10 = 2.7V
01 = 4.2V
00 = 4.5V
Power-on Reset Timer Value Select
11 = PWRT = 64 ms
10 = PWRT = 16 ms
01 = PWRT = 4 ms
00 = Power-up Timer disabled
Boot Segment Data RAM Code Protection (only present in dsPIC30F5011/5013/
6010A/6011A/6012A/6013A/6014A/6015)
11 = No Data RAM is reserved for Boot Segment
10 = Small-sized Boot RAM
01 = Medium-sized Boot RAM
00 = Large-sized Boot RAM
•
•
•
bit in the RCON register will have no effect)
in the RCON register)
put pins)
[128 bytes of RAM are reserved for Boot Segment]
[256 bytes of RAM are reserved for Boot Segment]
[512 bytes of RAM are reserved for Boot Segment in dsPIC30F5011/5013, and
1024 bytes in dsPIC30F6010A/6011A/6012A/6013A/6014A/6015]
Description
DS70102K-page 13