DSPIC30F3013T-20I/ML Microchip Technology, DSPIC30F3013T-20I/ML Datasheet - Page 17

• Manufacturer Part Number: DSPIC30F3013T-20I/ML
• Description: IC DSPIC MCU/DSP 24K 44QFN
• Manufacturer: Microchip Technology
• Series: dsPIC™ 30Fr

Specifications of DSPIC30F3013T-20I/ML

• Core Processor: dsPIC
• Core Size: 16-Bit
• Speed: 20 MIPS
• Connectivity: I²C, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, POR, PWM, WDT
• Number Of I /o: 20
• Program Memory Size: 24KB (8K x 24)
• Program Memory Type: FLASH
• Eeprom Size: 1K x 8
• Ram Size: 2K x 8
• Voltage - Supply (vcc/vdd): 2.5 V ~ 5.5 V
• Data Converters: A/D 10x12b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 44-QFN
• For Use With: DV164033 - KIT START EXPLORER 16 MPLAB ICD2DM240001 - BOARD DEMO PIC24/DSPIC33/PIC32
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

TABLE 5-10:
TABLE 5-11:
0xF80000
0xF80002
0xF80004
0xF80006
0xF80008
0xF8000A
0xF8000C
Note
0xF80000
0xF80002
0xF80004
0xF80006
0xF80008
0xF8000A
0xF8000C
Note
Address
Address
1:
2:
3:
1:
The FGS<2> bit is a read-only copy of the GCP bit (FGS<1>).
On the 2011, 2012, 3012, 3013, 3014 and 4013, these bits are reserved (read as ‘1’ and must be programmed as ‘1’).
Reserved bits read as ‘1’ and must be programmed as ‘1’.
On the 6011A, 6012A, 6013A and 6014A, these bits are reserved (read as ‘1’ and must be programmed as ‘1’).
FOSC
FWDT
FBORPOR
FBS
FSS
FGS
FICD
FOSC
FWDT
FBORPOR
FBS
FSS
FGS
FICD
Name
Name
dsPIC30F CONFIGURATION REGISTERS (FOR dsPIC30F2011/2012, dsPIC30F3010/3011/3012/3013/3014, dsPIC30F4013 AND
dsPIC30F5015/5016)
dsPIC30F CONFIGURATION REGISTERS (FOR dsPIC30F6010A/6011A/6012A/6013A/6014A AND dsPIC30F6015)
FWDTEN
FWDTEN
MCLREN
MCLREN
BKBUG
BKBUG
Bit 15
Bit 15
FCKSM<1:0>
FCKSM<1:0>
—
—
—
—
—
—
Bit 14
Bit 14
COE
COE
—
—
—
—
—
—
—
—
—
—
Bit 13
Bit 13
—
—
—
—
—
—
—
—
—
—
Reserved
Reserved
RBS<1:0>
RSS<1:0>
Bit 12
Bit 12
(2)
(2)
—
—
—
—
—
—
—
—
—
—
Bit 11
Bit 11
—
—
—
—
—
—
—
—
—
—
—
—
—
—
PWMPIN
PWMPIN
Bit 10
Bit 10
—
—
—
—
—
—
—
—
—
—
(1)
(1)
FOS<2:0>
FOS<2:0>
HPOL
HPOL
Bit 9
Bit 9
—
—
—
—
—
—
—
—
Reserved
ESS<1:0>
(1)
(1)
Reserved
LPOL
LPOL
Bit 8
Bit 8
(2)
EBS
—
—
—
—
—
—
(1)
(1)
(2)
BOREN
BOREN
Bit 7
Bit 7
—
—
—
—
—
—
—
—
—
—
—
—
Bit 6
Bit 6
—
—
—
—
—
—
—
—
—
—
—
—
—
—
Bit 5
Bit 5
FWPSA<1:0>
FWPSA<1:0>
—
—
—
—
—
—
—
—
—
—
BORV<1:0>
BORV<1:0>
Bit 4
Bit 4
—
—
—
—
—
—
—
—
Bit 3
Bit 3
—
—
—
—
—
—
Reserved
FPR<4:0>
FPR<4:0>
BSS<2:0>
SSS<2:0>
Bit 2
Bit 2
—
—
—
—
FWPSB<3:0>
FWPSB<3:0>
Reserved
Reserved
GSS<1:0>
(3)
Bit 1
GCP
Bit 1
(2)
(2)
FPWRT<1:0>
FPWRT<1:0>
ICS<1:0>
ICS<1:0>
GWRP
GWRP
BWRP
SWRP
Bit 0
Bit 0