DSPIC33FJ64GS406T-I/PT Microchip Technology, DSPIC33FJ64GS406T-I/PT Datasheet - Page 41

• Manufacturer Part Number: DSPIC33FJ64GS406T-I/PT
• Description: MCU/DSP 16BIT 64KB FLASH 64TQFP
• Manufacturer: Microchip Technology
• Series: dsPIC™ 33Fr

Specifications of DSPIC33FJ64GS406T-I/PT

• Program Memory Type: FLASH
• Program Memory Size: 64KB (64K x 8)
• Package / Case: 64-TFQFP
• Core Processor: dsPIC
• Core Size: 16-Bit
• Speed: 40 MIPs
• Connectivity: I²C, IrDA, LIN, SCI, SPI, UART/USART, USB
• Peripherals: Brown-out Detect/Reset, QEI, POR, PWM, WDT
• Number Of I /o: 58
• Ram Size: 8K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Data Converters: A/D 16x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Product: DSCs
• Data Bus Width: 16 bit
• Processor Series: DSPIC33F
• Core: dsPIC
• Numeric And Arithmetic Format: Fixed-Point or Floating-Point
• Instruction Set Architecture: Harvard
• Device Million Instructions Per Second: 40 MIPs
• Maximum Clock Frequency: 120 MHz
• Number Of Programmable I/os: 58
• Data Ram Size: 4 KB
• Operating Supply Voltage: 3.3 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: 52713-733, 52714-737, 53276-922, EWDSPIC
• Development Tools By Supplier: PG164130, DV164035, DV244005, DV164005, PG164120, DM240001, DV164033
• Interface Type: I2C, SPI, UART
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 10 bit, 16 Channel
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

3.5
The
dsPIC33FJ64GS406/606/608/610 ALU is 16 bits wide
and is capable of addition, subtraction, bit shifts and logic
operations. Unless otherwise mentioned, arithmetic
operations are 2’s complement in nature. Depending on
the operation, the ALU can affect the values of the Carry
(C), Zero (Z), Negative (N), Overflow (OV) and Digit Carry
(DC) Status bits in the SR register. The C and DC Status
bits operate as Borrow and Digit Borrow bits, respectively,
for subtraction operations.
The ALU can perform 8-bit or 16-bit operations,
depending on the mode of the instruction that is used.
Data for the ALU operation can come from the W
register array or data memory, depending on the
addressing mode of the instruction. Likewise, output
data from the ALU can be written to the W register array
or a data memory location.
Refer to the “16-bit MCU and DSC Programmer’s Ref-
erence Manual” (DS70157) for information on the SR
bits affected by each instruction.
The
dsPIC33FJ64GS406/606/608/610
hardware support for both multiplication and division. This
includes a dedicated hardware multiplier and support
hardware for 16-bit-divisor division.
3.5.1
Using the high-speed, 17-bit x 17-bit multiplier of the
DSP engine, the ALU supports unsigned, signed or
mixed sign operation in several MCU multiplication
modes:
• 16-bit x 16-bit signed
• 16-bit x 16-bit unsigned
• 16-bit signed x 5-bit (literal) unsigned
• 16-bit unsigned x 16-bit unsigned
• 16-bit unsigned x 5-bit (literal) unsigned
• 16-bit unsigned x 16-bit signed
• 8-bit unsigned x 8-bit unsigned
 2010 Microchip Technology Inc.
dsPIC33FJ32GS406/606/608/610 and dsPIC33FJ64GS406/606/608/610
Arithmetic Logic Unit (ALU)
dsPIC33FJ32GS406/606/608/610
dsPIC33FJ32GS406/606/608/610
MULTIPLIER
CPU
incorporates
and
and
Preliminary
3.5.2
The divide block supports 32-bit/16-bit and 16-bit/16-bit
signed and unsigned integer divide operations with the
following data sizes:
• 32-bit signed/16-bit signed divide
• 32-bit unsigned/16-bit unsigned divide
• 16-bit signed/16-bit signed divide
• 16-bit unsigned/16-bit unsigned divide
The quotient for all divide instructions ends up in W0 and
the remainder in W1. 16-bit signed and unsigned DIV
instructions can specify any W register for both the 16-bit
divisor (Wn) and any W register (aligned) pair
(W(m + 1):Wm) for the 32-bit dividend. The divide
algorithm takes one cycle per bit of divisor, so both 32-bit/
16-bit and 16-bit/16-bit instructions take the same
number of cycles to execute.
3.6
The DSP engine consists of a high-speed, 17-bit x
17-bit multiplier, a barrel shifter and a 40-bit adder/
subtracter (with two target accumulators, round and
saturation logic).
The
dsPIC33FJ64GS406/606/608/610
instruction flow architecture; therefore, concurrent opera-
tion of the DSP engine with MCU instruction flow is not
possible. However, some MCU ALU and DSP engine
resources can be used concurrently by the same instruc-
tion (for example, ED, EDAC).
The
accumulator-to-accumulator operations that require no
additional data. These instructions are ADD, SUB and
NEG.
The DSP engine has options selected through bits in
the CPU Core Control register (CORCON), as listed
below:
• Fractional or integer DSP multiply (IF)
• Signed or unsigned DSP multiply (US)
• Conventional or convergent rounding (RND)
• Automatic saturation on/off for ACCA (SATA)
• Automatic saturation on/off for ACCB (SATB)
• Automatic saturation on/off for writes to data
• Accumulator Saturation mode selection (ACC-
A block diagram of the DSP engine is shown in
Figure 3-3.
memory (SATDW)
SAT)
DSP
DSP Engine
dsPIC33FJ32GS406/606/608/610
DIVIDER
engine
can
also
is
perform
DS70591C-page 41
a
single-cycle
inherent
and