ATTINY84-15MZ Atmel, ATTINY84-15MZ Datasheet - Page 167

• Manufacturer Part Number: ATTINY84-15MZ
• Description: MCU AVR 8K FLASH 15MHZ 20-QFN
• Manufacturer: Atmel
• Series: AVR® ATtinyr

Specifications of ATTINY84-15MZ

• Package / Case: 20-QFN Exposed Pad
• Voltage - Supply (vcc/vdd): 2.7 V ~ 5.5 V
• Operating Temperature: -40°C ~ 125°C
• Speed: 16MHz
• Number Of I /o: 12
• Eeprom Size: 512 x 8
• Core Processor: AVR
• Program Memory Type: FLASH
• Ram Size: 512 x 8
• Program Memory Size: 8KB (8K x 8)
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Peripherals: Brown-out Detect/Reset, POR, PWM, WDT
• Connectivity: USI
• Core Size: 8-Bit
• Processor Series: ATTINY8x
• Core: AVR8
• Data Bus Width: 8 bit
• Data Ram Size: 512 B
• Interface Type: SPI, UART
• Maximum Clock Frequency: 16 MHz
• Number Of Programmable I/os: 12
• Number Of Timers: 2
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: EWAVR, EWAVR-BL
• Development Tools By Supplier: ATAVRDRAGON, ATSTK500, ATSTK600, ATAVRISP2, ATAVRONEKIT
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 10 bit, 8 Channel
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

21.6.1
7701D–AVR–09/10
Serial Programming Algorithm
When writing serial data to the Atmel
edge of SCK.
When reading data from the Atmel ATtiny24/44/84, data are clocked on the falling edge of
SCK. See
To program and verify the Atmel ATtiny24/44/84 in the serial programming mode, the following
sequence is recommended (see four-byte instruction formats in
1. Power-up sequence:
2. Wait for at least 20ms and enable serial programming by sending the Programming
3. The serial programming instructions will not work if the communication is out of syn-
4. The flash is programmed one page at a time. The memory page is loaded one byte at
5. A: The EEPROM array is programmed one byte at a time by supplying the address and
6. Any memory location can be verified by using the Read instruction which returns the
7. At the end of the programming session, RESET can be set high to commence normal
Apply power between V
tems, the programmer can not guarantee that SCK is held low during power-up. In this
case, RESET must be given a positive pulse of at least two CPU clock cycles duration
after SCK has been set to “0”.
Enable serial instruction to pin MOSI.
chronization. When in sync, the second byte (0x53) will echo back when issuing the
third byte of the programming enable instruction. Regardless of whether the echo is
correct or not, all four bytes of the instruction must be transmitted. If the 0x53 did not
echo back, give RESET a positive pulse and issue a new programming enable
command.
a time by supplying the five LSBs of the address and data together with the load pro-
gram memory page instruction. To ensure correct loading of the page, the data low
byte must be loaded before the data high byte is applied for a given address. The pro-
gram memory page is stored by loading the write program memory page instruction
with the three MSBs of the address. If polling (RDY/BSY) is not used, the user must
wait at least tWD_FLASH before issuing the next page. (See
168.) Accessing the serial programming interface before the Flash write operation
completes can result in incorrect programming.
data together with the appropriate Write instruction. An EEPROM memory location is
first automatically erased before new data are written. If polling (RDY/BSY) is not used,
the user must wait at least t
on page
grammed.
B: The EEPROM array is programmed one page at a time. The Memory page is
loaded one byte at a time by supplying the two LSBs of the address and data together
with the Load EEPROM Memory Page instruction. The EEPROM Memory Page is
stored by loading the Write EEPROM Memory Page Instruction with the four MSBs of
the address. When using EEPROM page access only byte locations loaded with the
Load EEPROM Memory Page instruction is altered. The remaining locations remain
unchanged. If polling (RDY/BSY) is not used, the used must wait at least t
before issuing the next page (See
no 0xFF in the data file(s) need to be programmed.
content at the selected address at serial output MISO.
operation.
Figure 22-3
168.) In a chip erased device, no 0xFFs in the data file(s) need to be pro-
and
Atmel ATtiny24/44/84 [Preliminary]
Figure 22-4
CC
and GND while RESET and SCK are set to “0”. In some sys-
WD_EEPROM
®
Table 21-10 on page
for timing details.
AVR
before issuing the next byte. (See
®
ATtiny24/44/84, data are clocked on the rising
168). In a chip-erased device,
Table
Table 21-10 on page
21-11):
Table 21-10
WD_EEPROM
167