ATTINY84-15MZ Atmel, ATTINY84-15MZ Datasheet - Page 46

• Manufacturer Part Number: ATTINY84-15MZ
• Description: MCU AVR 8K FLASH 15MHZ 20-QFN
• Manufacturer: Atmel
• Series: AVR® ATtinyr

Specifications of ATTINY84-15MZ

• Package / Case: 20-QFN Exposed Pad
• Voltage - Supply (vcc/vdd): 2.7 V ~ 5.5 V
• Operating Temperature: -40°C ~ 125°C
• Speed: 16MHz
• Number Of I /o: 12
• Eeprom Size: 512 x 8
• Core Processor: AVR
• Program Memory Type: FLASH
• Ram Size: 512 x 8
• Program Memory Size: 8KB (8K x 8)
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Peripherals: Brown-out Detect/Reset, POR, PWM, WDT
• Connectivity: USI
• Core Size: 8-Bit
• Processor Series: ATTINY8x
• Core: AVR8
• Data Bus Width: 8 bit
• Data Ram Size: 512 B
• Interface Type: SPI, UART
• Maximum Clock Frequency: 16 MHz
• Number Of Programmable I/os: 12
• Number Of Timers: 2
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: EWAVR, EWAVR-BL
• Development Tools By Supplier: ATAVRDRAGON, ATSTK500, ATSTK600, ATAVRISP2, ATAVRONEKIT
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 10 bit, 8 Channel
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

46
Atmel ATtiny24/44/84 [Preliminary]
If WDE is set, WDIE is automatically cleared by hardware when a time-out occurs. This is use-
ful for keeping the Watchdog Reset security while using the interrupt. After the WDIE bit is
cleared, the next time-out will generate a reset. To avoid the Watchdog Reset, WDIE must be
set after each interrupt.
Table 9-3.
• Bit 4 – WDCE: Watchdog Change Enable
This bit must be set when the WDE bit is written to logical zero. Otherwise, the watchdog will
not be disabled. Once written to logical one, hardware will clear this bit after four clock cycles.
See the description of the WDE bit for a watchdog disable procedure. This bit must also be set
when changing the prescaler bits. See
the Watchdog Timer” on page
• Bit 3 – WDE: Watchdog Enable
When the WDE is written to logical one, the watchdog timer is enabled, and if the WDE is writ-
ten to logical zero, the watchdog timer function is disabled. WDE can only be cleared if the
WDCE bit has logic level one. To disable an enabled watchdog timer, the following procedure
must be followed:
1. In the same operation, write a logical one to WDCE and WDE. A logical one must be
2. Within the next four clock cycles, write a logical zero to WDE. This disables the
In safety level 2, it is not possible to disable the Watchdog Timer, even with the algorithm
described above. See
Timer” on page
In safety level 1, WDE is overridden by WDRF in MCUSR. See
ter” on page 45
set. To clear WDE, WDRF must be cleared before disabling the Watchdog with the procedure
described above. This feature ensures multiple resets during conditions causing failure, and a
safe start-up after the failure.
Note:
• Bits 5, 2..0 – WDP3..0: Watchdog Timer Prescaler 3, 2, 1, and 0
The WDP3..0 bits determine the Watchdog Timer prescaling when the Watchdog Timer is
enabled. The different prescaling values and their corresponding Timeout Periods are shown
in
Table 9-4 on page
WDE
written to WDE even though it is set to logical one before the disable operation starts.
watchdog.
0
0
1
1
If the watchdog timer is not going to be used in the application, it is important to go through a
watchdog disable procedure in the initialization of the device. If the Watchdog is accidentally
enabled, for example by a runaway pointer or brown-out condition, the device will be reset,
which in turn will lead to a new watchdog reset. To avoid this situation, the application software
should always clear the WDRF flag and the WDE control bit in the initialization routine.
Watchdog Timer Configuration
44.
for description of WDRF. This means that WDE is always set when WDRF is
WDIE
0
1
0
1
47.
“Timed Sequences for Changing the Configuration of the Watchdog
Watchdog Timer State
Stopped
Running
Running
Running
44.
“Timed Sequences for Changing the Configuration of
“MCUSR – MCU Status Regis-
Action on Time-out
None
Interrupt
Reset
Interrupt
7701D–AVR–09/10