PIC18F26J50-I/SP Microchip Technology, PIC18F26J50-I/SP Datasheet - Page 424

• Manufacturer Part Number: PIC18F26J50-I/SP
• Description: IC PIC MCU FLASH 64K 2V 28-DIP
• Manufacturer: Microchip Technology
• Series: PIC® XLP™ 18Fr

Specifications of PIC18F26J50-I/SP

• Program Memory Type: FLASH
• Program Memory Size: 64KB (32K x 16)
• Package / Case: 28-DIP (0.300", 7.62mm)
• Core Processor: PIC
• Core Size: 8-Bit
• Speed: 48MHz
• Connectivity: I²C, SPI, UART/USART, USB
• Peripherals: Brown-out Detect/Reset, DMA, POR, PWM, WDT
• Number Of I /o: 16
• Ram Size: 3.8K x 8
• Voltage - Supply (vcc/vdd): 2.15 V ~ 3.6 V
• Data Converters: A/D 10x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Processor Series: PIC18F
• Core: PIC
• Data Bus Width: 8 bit
• Data Ram Size: 3776 B
• Interface Type: EUSART/I2C/SPI
• Maximum Clock Frequency: 48 MHz
• Number Of Timers: 5
• Maximum Operating Temperature: + 85 C
• Mounting Style: Through Hole
• 3rd Party Development Tools: 52715-96, 52716-328, 52717-734, 52712-325, EWPIC18
• Development Tools By Supplier: PG164130, DV164035, DV244005, DV164005, PG164120, DM183032, DV164136, MA180024, DM183022
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 10-ch x 10-bit
• Package: 28SPDIP
• Device Core: PIC
• Family Name: PIC18
• Maximum Speed: 48 MHz
• Operating Supply Voltage: 2.5|3.3 V
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: AC164322 - MODULE SOCKET MPLAB PM3 28/44QFN
• Eeprom Size: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

PIC18F46J50 FAMILY
REGISTER 26-11: WDTCON: WATCHDOG TIMER CONTROL REGISTER (ACCESS FC0h)
TABLE 26-3:
DS39931C-page 424
RCON
WDTCON
Legend: — = unimplemented, read as ‘0’. Shaded cells are not used by the Watchdog Timer.
bit 7
Legend:
R = Readable bit
-n = Value at POR
bit 7
bit 6
bit 5
bit 4
bit 3
bit 2
bit 1
bit 0
Note 1:
REGSLP
Name
R/W-1
2:
This bit has no effect if the Configuration bit, WDTEN, is enabled.
Not available on devices where the on-chip voltage regulator is disabled (“LF” devices).
REGSLP LVDSTAT ULPLVL
REGSLP: Voltage Regulator Low-Power Operation Enable bit
1 = On-chip regulator enters low-power operation when device enters Sleep mode
0 = On-chip regulator is active even in Sleep mode
LVDSTAT: Low-Voltage Detect Status bit
1 = V
0 = V
ULPLVL: Ultra Low-Power Wake-up Output bit (not valid unless ULPEN = 1)
1 = Voltage on RA0 > ~0.5V
0 = Voltage on RA0 < ~0.5V
Unimplemented: Read as ‘0’
DS: Deep Sleep Wake-up Status bit (used in conjunction with RCON, POR and BOR bits to determine
Reset source)
1 = If the last exit from Reset was caused by a normal wake-up from Deep Sleep
0 = If the last exit from Reset was not due to a wake-up from Deep Sleep
ULPEN: Ultra Low-Power Wake-up Module Enable bit
1 = Ultra Low-Power Wake-up module is enabled; ULPLVL bit indicates comparator output
0 = Ultra Low-Power Wake-up module is disabled
ULPSINK: Ultra Low-Power Wake-up Current Sink Enable bit
1 = Ultra low-power wake-up current sink is enabled (if ULPEN = 1)
0 = Ultra low-power wake-up current sink is disabled
SWDTEN: Software Controlled Watchdog Timer Enable bit
1 = Watchdog Timer is on
0 = Watchdog Timer is off
LVDSTAT
IPEN
Bit 7
SUMMARY OF WATCHDOG TIMER REGISTERS
R-x
DDCORE
DDCORE
(2)
Bit 6
—
> 2.45V nominal
< 2.45V nominal
(2)
W = Writable bit
‘1’ = Bit is set
ULPLVL
R-x
Bit 5
CM
U-0
Bit 4
—
RI
—
(2)
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared
Bit 3
TO
DS
R/W-0
DS
ULPEN ULPSINK SWDTEN
Bit 2
PD
(1)
ULPEN
R/W-0
Bit 1
POR
© 2009 Microchip Technology Inc.
x = Bit is unknown
ULPSINK
R/W-0
Bit 0
BOR
Reset Values
SWDTEN
on Page:
R/W-0
64
64
bit 0
(1)