AT89S8253-24AU Atmel, AT89S8253-24AU Datasheet - Page 22

• Manufacturer Part Number: AT89S8253-24AU
• Description: IC MCU 12K FLASH 24MHZ 44-TQFP
• Manufacturer: Atmel
• Series: 89Sr

Specifications of AT89S8253-24AU

• Core Processor: 8051
• Core Size: 8-Bit
• Speed: 24MHz
• Connectivity: SPI, UART/USART
• Peripherals: POR, WDT
• Number Of I /o: 32
• Program Memory Size: 12KB (12K x 8)
• Program Memory Type: FLASH
• Eeprom Size: 2K x 8
• Ram Size: 256 x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 5.5 V
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 44-TQFP, 44-VQFP
• Processor Series: AT89x
• Core: 8051
• Data Bus Width: 8 bit
• Data Ram Size: 256 B
• Interface Type: SPI/UART
• Maximum Clock Frequency: 24 MHz
• Number Of Programmable I/os: 32
• Number Of Timers: 3
• Operating Supply Voltage: 2.7 V to 5.5 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: PK51, CA51, A51, ULINK2
• Development Tools By Supplier: AT89ISP
• Minimum Operating Temperature: - 40 C
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Data Converters: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

Table 13-1.
Table 13-2.
22
PCON Address = 87H
Bit Addressable
Bit
Symbol
SMOD1
SMOD0
POF
GF1, GF0
PD
IDL
SCON Address = 98H
Bit Addressable
Bit
Symbol
FE
SM0
SM1
SM2
REN
TB8
RB8
TI
RI
(SMOD0 = 0/1)
AT89S8253
SM0/FE
SMOD1
Function
Framing error bit. This bit is set by the receiver when an invalid stop bit is detected. The FE bit is not cleared by valid
frames but should be cleared by software. The SMOD0 bit must be set to enable access to the FE bit. FE will be set
regardless of the state of SMOD0.
Serial Port Mode Bit 0, (SMOD0 must = 0 to access bit SM0)
Serial Port Mode Bit 1
Enables the Automatic Address Recognition feature in modes 2 or 3. If SM2 = 1 then Rl will not be set unless the received
9th data bit (RB8) is 1, indicating an address, and the received byte is a Given or Broadcast Address. In mode 1, if SM2 =
1 then Rl will not be activated unless a valid stop bit was received, and the received byte is a Given or Broadcast Address.
In Mode 0, SM2 should be 0.
Enables serial reception. Set by software to enable reception. Clear by software to disable reception.
The 9th data bit that will be transmitted in modes 2 and 3. Set or clear by software as desired.
In modes 2 and 3, the 9th data bit that was received. In mode 1, if SM2 = 0, RB8 is the stop bit that was received. In mode
0, RB8 is not used.
Transmit interrupt flag. Set by hardware at the end of the 8th bit time in mode 0, or at the beginning of the stop bit in the
other modes, in any serial transmission. Must be cleared by software.
Receive interrupt flag. Set by hardware at the end of the 8th bit time in mode 0, or halfway through the stop bit time in the
other modes, in any serial reception (except see SM2). Must be cleared by software.
7
7
Function
Double Baud Rate bit. Doubles the baud rate of the UART in Modes 1, 2, or 3.
Frame Error Select. When SMOD0 = 1, SCON.7 is SM0. When SMOD0 = 1, SCON.7 is FE. Note that FE will be set after
a frame error regardless of the state of SMOD0.
Power Off Flag. POF is set to “1” during power up (i.e. cold reset). It can be set or reset under software control and is not
affected by RST (i.e. warm reset).
General-purpose Flags
Power-down bit. Setting this bit activates power-down operation.
Idle Mode bit. Setting this bit activates Idle mode operation
PCON – Power Control Register
SCON – Serial Port Control Register
SM0
0
0
1
1
(1)
SMOD0
SM1
6
6
SM1
0
1
0
1
SM2
–
5
5
Mode
0
1
2
3
POF
REN
4
4
shift register
Description
8-bit UART
9-bit UART
9-bit UART
GF1
TB8
3
3
f
osc
GF0
RB8
Baud Rate
2
2
/64 or f
variable
variable
f
osc
/12
osc
Reset Value = 0000 0000B
(2)
Reset Value = 00xx 0000B
/32
PD
T1
1
1
IDL
3286P–MICRO–3/10
RI
0
0