ATMEGA329P-20MN Atmel, ATMEGA329P-20MN Datasheet - Page 41

• Manufacturer Part Number: ATMEGA329P-20MN
• Description: IC MCU AVR 32K 20MHZ 64QFN
• Manufacturer: Atmel
• Series: AVR® ATmegar

Specifications of ATMEGA329P-20MN

• Core Processor: AVR
• Core Size: 8-Bit
• Speed: 20MHz
• Connectivity: SPI, UART/USART, USI
• Peripherals: Brown-out Detect/Reset, LCD, POR, PWM, WDT
• Number Of I /o: 54
• Program Memory Size: 32KB (16K x 16)
• Program Memory Type: FLASH
• Eeprom Size: 1K x 8
• Ram Size: 2K x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 5.5 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 64-MLF®, 64-QFN
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

9.10.6
9.10.7
8021G–AVR–03/11
Port Pins
JTAG Interface and On-chip Debug System
When entering a sleep mode, all port pins should be configured to use minimum power. The
most important is then to ensure that no pins drive resistive loads. In sleep modes where both
the I/O clock (clk
be disabled. This ensures that no power is consumed by the input logic when not needed. In
some cases, the input logic is needed for detecting wake-up conditions, and it will then be
enabled. Refer to the section
which pins are enabled. If the input buffer is enabled and the input signal is left floating or have
an analog signal level close to V
For analog input pins, the digital input buffer should be disabled at all times. An analog signal
level close to V
input buffers can be disabled by writing to the Digital Input Disable Registers (DIDR1 and
DIDR0). Refer to
Input Disable Register 0” on page 229
If the On-chip debug system is enabled by the OCDEN Fuse and the chip enter Power down or
Power save sleep mode, the main clock source remains enabled. In these sleep modes, this will
contribute significantly to the total current consumption. There are three alternative ways to
avoid this:
• Disable OCDEN Fuse.
• Disable JTAGEN Fuse.
• Write one to the JTD bit in MCUCR.
The TDO pin is left floating when the JTAG interface is enabled while the JTAG TAP controller is
not shifting data. If the hardware connected to the TDO pin does not pull up the logic level,
power consumption will increase. Note that the TDI pin for the next device in the scan chain con-
tains a pull-up that avoids this problem. Writing the JTD bit in the MCUCR register to one or
leaving the JTAG fuse unprogrammed disables the JTAG interface.
CC
I/O
”DIDR1 – Digital Input Disable Register 1” on page 212
/2 on an input pin can cause significant current even in active mode. Digital
) and the ADC clock (clk
”Digital Input Enable and Sleep Modes” on page 67
CC
/2, the input buffer will use excessive power.
for details.
ADC
) are stopped, the input buffers of the device will
ATmega329P/3290P
and
”DIDR0 – Digital
for details on
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