DSPIC30F4013T-20E/ML Microchip Technology, DSPIC30F4013T-20E/ML Datasheet - Page 3

• Manufacturer Part Number: DSPIC30F4013T-20E/ML
• Description: IC DSPIC MCU/DSP 48K 44QFN
• Manufacturer: Microchip Technology
• Series: dsPIC™ 30Fr

Specifications of DSPIC30F4013T-20E/ML

• Core Processor: dsPIC
• Core Size: 16-Bit
• Speed: 20 MIPS
• Connectivity: CAN, I²C, SPI, UART/USART
• Peripherals: AC'97, Brown-out Detect/Reset, I²S, POR, PWM, WDT
• Number Of I /o: 30
• Program Memory Size: 48KB (16K x 24)
• Program Memory Type: FLASH
• Eeprom Size: 1K x 8
• Ram Size: 2K x 8
• Voltage - Supply (vcc/vdd): 2.5 V ~ 5.5 V
• Data Converters: A/D 13x12b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 125°C
• Package / Case: 44-QFN
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

TABLE 2:
© 2010 Microchip Technology Inc.
Operations
Note 1:
Module
Voltage
Detect
(LVD)
Sleep
Timer
Mode
Low-
PSV
CAN
ADC
PLL
I
I/O
I
I
I
I
2
2
2
2
2
C
C
C
C
C
Only those issues indicated in the last column apply to the current silicon revision.
Consumption
Bus Collision
Sleep Mode
Slave Mode
Multiplexed
Lock Status
Addressing
Addressing
Addressing
Message
Feature
with IC1
in Sleep
Port Pin
SILICON ISSUE SUMMARY (CONTINUED)
Current
Filters
10-bit
10-bit
10-bit
Mode
—
—
bit
—
Number
Item
16.
17.
18.
19.
20.
21.
22.
23.
24.
25.
26.
27.
28.
The external Low-Voltage Detect (LVD) module is not connected
to the AN2 Pad.
Execution of the Sleep instruction (PWRSAV #0) may cause
incorrect program operation after the device wakes up from
Sleep. The current consumption during Sleep may also increase
beyond the specifications listed in the device data sheet.
The I
I
The Port I/O pin multiplexed with the Input Capture 1 (IC1)
function cannot be used as a digital input pin when the UART
auto-baud feature is enabled.
When the I
the same address bits (A10 and A9) as other I
A10 and A9 bits may not work as expected.
Clock switching prevents the device from waking up from Sleep.
The PLL LOCK Status bit (OSCCON<5>) can occasionally get
cleared and generate an oscillator failure trap even when the
PLL is still locked and functioning correctly.
An address error trap occurs in certain addressing modes when
accessing the first four bytes of any PSV page.
The 10-bit slave does not set the RBF flag or load the I2CxRCV
register on address match if the Least Significant bits (LSbs) of
the address are the same as the 7-bit reserved addresses.
When the I
address of 0x102, the I2CxRCV register content for the lower
address byte is 0x01 rather than 0x02.
When the I
generates a glitch on the SDA and SCL pins, causing a false
communication start in a single-master configuration or a bus
collision in a multi-master configuration.
CAN receive filters 3, 4 and 5 may not work for a given
combination of instruction cycle speed and CAN bit time quanta.
If the ADC module is in an enabled state when the device enters
Sleep Mode, the power-down current (I
exceed the device data sheet specifications.
2
C slave.
2
C module loses incoming data bytes when operating as an
2
2
2
C module is configured for 10-bit addressing using
C module is configured as a 10-bit slave with an
C module is enabled, the dsPIC
Issue Summary
dsPIC30F3014/4013
PD
) of the device may
®
DSC device
2
C devices, the
DS80455D-page 3
Revisions
A1
Affected
X
X
X
X
X
X
X
X
X
X
X
X
X
A2
X
X
X
X
X
X
X
X
X
X
X
X
(1)