IC DSPIC MCU/DSP 48K 44TQFP

DSPIC30F4013-20E/PT

Manufacturer Part NumberDSPIC30F4013-20E/PT
DescriptionIC DSPIC MCU/DSP 48K 44TQFP
ManufacturerMicrochip Technology
SeriesdsPIC™ 30F
DSPIC30F4013-20E/PT datasheets
 

Specifications of DSPIC30F4013-20E/PT

Program Memory TypeFLASHProgram Memory Size48KB (16K x 24)
Package / Case44-TQFP, 44-VQFPCore ProcessordsPIC
Core Size16-BitSpeed20 MIPS
ConnectivityCAN, I²C, SPI, UART/USARTPeripheralsAC'97, Brown-out Detect/Reset, I²S, POR, PWM, WDT
Number Of I /o30Eeprom Size1K x 8
Ram Size2K x 8Voltage - Supply (vcc/vdd)2.5 V ~ 5.5 V
Data ConvertersA/D 13x12bOscillator TypeInternal
Operating Temperature-40°C ~ 125°CProductDSCs
Data Bus Width16 bitProcessor SeriesDSPIC30F
CoredsPICMaximum Clock Frequency20 MHz
Number Of Programmable I/os30Data Ram Size2 KB
Maximum Operating Temperature+ 125 CMounting StyleSMD/SMT
3rd Party Development Tools52713-733, 52714-737, 53276-922, EWDSPICDevelopment Tools By SupplierPG164130, DV164035, DV244005, DV164005, PG164120, ICE4000, DM240002, DM300018, DM330011
Minimum Operating Temperature- 40 CPackage44TQFP
Device CoredsPICFamily NamedsPIC30
Maximum Speed20 MHzOperating Supply Voltage3.3|5 V
Interface TypeCAN/I2C/SPI/UARTOn-chip Adc13-chx12-bit
Number Of Timers5Core Frequency20MHz
Embedded Interface TypeCAN, I2C, SPI, UARTNo. Of I/o's30
Flash Memory Size48KBSupply Voltage Range2.5V To 5.5V
Rohs CompliantYesLead Free Status / RoHS StatusLead free / RoHS Compliant
For Use WithAC30F006 - MODULE SKT FOR DSPIC30F 44TQFPOther namesDSPIC30F401320EPT
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dsPIC30F Flash Programming Specification
1.0
OVERVIEW AND SCOPE
This document defines the programming specification
for the dsPIC30F family of Digital Signal Controllers
(DSCs). The programming specification is required
only for the developers of third-party tools that are used
to program dsPIC30F devices. Customers using
dsPIC30F devices should use development tools that
already provide support for device programming.
This document includes programming specifications
for the following devices:
• dsPIC30F2010/2011/2012
• dsPIC30F3010/3011/3012/3013/ 3014
• dsPIC30F4011/4012/4013
• dsPIC30F5011/5013/5015/5016
• dsPIC30F6010/6011/6012/6013/6014/6015
• dsPIC30F6010A/6011A/6012A/6013A/6014A
2.0
PROGRAMMING OVERVIEW
OF THE dsPIC30F
The dsPIC30F family of DSCs contains a region of on-
chip memory used to simplify device programming.
This region of memory can store a programming
executive,
which
allows
the
dsPIC30F
programmed faster than the traditional means. Once
the programming executive is stored to memory by an
external programmer (such as Microchip’s MPLAB
®
ICD 2, MPLAB PM3, PRO MATE
II, or MPLAB REAL
ICE™), it can then interact with the external
programmer to efficiently program devices.
The programmer and programming executive have a
master-slave relationship, where the programmer is
the master programming device and the programming
executive is the slave, as illustrated in
FIGURE 2-1:
OVERVIEW OF dsPIC30F
PROGRAMMING
Programmer
2
Programming
Executive
On-chip Memory
dsPIC30F Device
© 2010 Microchip Technology Inc.
Two different methods are used to program the chip in
the user’s system. One method uses the Enhanced In-
Circuit Serial Programming™ (Enhanced ICSP™)
protocol and works with the programming executive.
The other method uses In-Circuit Serial Programming
(ICSP) protocol and does not use the programming
executive.
The Enhanced ICSP protocol uses the faster, high-
voltage
method
programming executive. The programming executive
provides all the necessary functionality to erase,
program and verify the chip through a small command
set. The command set allows the programmer to
program the dsPIC30F without having to deal with the
low-level programming protocols of the chip.
The ICSP programming method does not use the
programming executive. It provides native, low-level
programming capability to erase, program and verify
the chip. This method is significantly slower because it
uses control codes to serially execute instructions on
the dsPIC30F device.
This specification describes the ICSP and Enhanced
ICSP
programming
“Programming Executive Application”
the
programming
to
be
Section 5.0 “Device Programming”
application programmer’s interface for the host
programmer.
®
describes the ICSP programming method.
2.1
Hardware Requirements
In ICSP or Enhanced ICSP mode, the dsPIC30F
requires two programmable power supplies: one for
V
and one for MCLR. For Bulk Erase programming,
DD
which is required for erasing code protection bits, V
Figure
2-1.
must be greater than 4.5 volts. Refer to
“AC/DC Characteristics and Timing Requirements”
for additional hardware parameters.
dsPIC30F
that
takes
advantage
of
methods.
Section 3.0
describes
executive
application
describes its
Section 11.0
“ICSP™
Mode”
Section 13.0
DS70102K-page 1
the
and
DD

DSPIC30F4013-20E/PT Summary of contents

  • Page 1

    ... Programming Executive On-chip Memory dsPIC30F Device © 2010 Microchip Technology Inc. Two different methods are used to program the chip in the user’s system. One method uses the Enhanced In- Circuit Serial Programming™ (Enhanced ICSP™) protocol and works with the programming executive. ...

  • Page 2

    ... 0x000000-0x001FFE (4K) dsPIC30F3010 0x000000-0x003FFE (8K) dsPIC30F3011 0x000000-0x003FFE (8K) dsPIC30F3012 0x000000-0x003FFE (8K) dsPIC30F3013 0x000000-0x003FFE (8K) dsPIC30F3014 0x000000-0x003FFE (8K) dsPIC30F4011 0x000000-0x007FFE (16K) dsPIC30F4012 0x000000-0x007FFE (16K) dsPIC30F4013 0x000000-0x007FFE (16K) dsPIC30F5011 0x000000-0x00AFFE (22K) dsPIC30F5013 0x000000-0x00AFFE (22K) dsPIC30F5015 0x000000-0x00AFFE (22K) dsPIC30F5016 0x000000-0x00AFFE (22K) dsPIC30F6010 0x000000-0x017FFE (48K) dsPIC30F6010A 0x000000-0x017FFE (48K) dsPIC30F6011 0x000000-0x015FFE (44K) ...

  • Page 3

    ... FIGURE 2-2: PROGRAM MEMORY MAP Note: The address boundaries for user Flash code memory and data EEPROM are device-dependent. © 2010 Microchip Technology Inc. 000000 User Flash Code Memory (48K x 24-bit) 017FFE 018000 Reserved 7FEFFE 7FF000 Data EEPROM (2K x 16-bit) 7FFFFE ...

  • Page 4

    ... Address Section 5.0 0x8005BE Is Application ID 0xBB? Prog. Executive is Resident in Memory Finish executive must be Section 12.0 “Programming the Memory”. describes the process Section 11.13 describes the CONFIRMING PRESENCE OF THE PROGRAMMING EXECUTIVE No Yes Prog. Executive must be Programmed © 2010 Microchip Technology Inc. ...

  • Page 5

    ... Enhanced ICSP mode is exited. If any of the verifications fail, the procedure should be repeated, starting from the Chip Erase. © 2010 Microchip Technology Inc. If Advanced Security features are enabled, then individual Segment Erase operations need to be performed, based on user selections (i.e., based on the specific needs of the user application) ...

  • Page 6

    ... BLANK’ response is returned. The READD command is used to read the Configuration registers determined that the device is not blank, it must be erased (see Section 5.3 “Chip attempting to program the chip. Section 5.7 Programming”). Erase”) before © 2010 Microchip Technology Inc. ...

  • Page 7

    ... 4K 128 dsPIC30F3010 8K 256 dsPIC30F3011 8K 256 dsPIC30F3012 8K 256 dsPIC30F3013 8K 256 dsPIC30F3014 8K 256 dsPIC30F4011 16K 512 dsPIC30F4012 16K 512 dsPIC30F4013 16K 512 dsPIC30F5011 22K 704 dsPIC30F5013 22K 704 dsPIC30F5015 22K 704 dsPIC30F5016 22K 704 dsPIC30F6010 48K 1536 dsPIC30F6010A 48K 1536 dsPIC30F6011 44K 1408 ...

  • Page 8

    ... Size (Words) dsPIC30F2010 512 dsPIC30F2011 0 dsPIC30F2012 0 dsPIC30F3010 512 dsPIC30F3011 512 dsPIC30F3012 512 dsPIC30F3013 512 dsPIC30F3014 512 dsPIC30F4011 512 dsPIC30F4012 512 dsPIC30F4013 512 dsPIC30F5011 512 dsPIC30F5013 512 dsPIC30F5015 512 dsPIC30F5016 512 dsPIC30F6010 2048 dsPIC30F6010A 2048 dsPIC30F6011 1024 dsPIC30F6011A 1024 dsPIC30F6012 2048 dsPIC30F6012A ...

  • Page 9

    ... XT – XT Crystal Oscillator mode (4 MHz-10 MHz crystal) 001x = HS – HS Crystal Oscillator mode (10 MHz-25 MHz crystal) 000x = XTL – XTL Crystal Oscillator mode (200 kHz-4 MHz crystal) © 2010 Microchip Technology Inc. The FOSC Configuration register has three different register descriptions, based on the device. The FOSC ...

  • Page 10

    ... HS – HS Crystal Oscillator mode (10 MHz-25 MHz crystal) 0001 = FRC w/PLL 4x – Internal fast RC oscillator with 4x PLL. OSC2 pin is I/O 0000 = XTL – XTL Crystal Oscillator mode (200 kHz-4 MHz crystal) DS70102K-page 10 Description (F /4) OSC /4) OSC © 2010 Microchip Technology Inc. ...

  • Page 11

    ... TABLE 5-6: FOSC CONFIGURATION BITS DESCRIPTION FOR dsPIC30F2011/2012, dsPIC30F3010/3011/3012/3013/3014, dsPIC30F4013, dsPIC30F5015/5016, dsPIC30F6010A/6011A/6012A/6013A/6014A AND dsPIC30F6015 Bit Field Register FCKSM<1:0> FOSC Clock Switching Mode 1x = Clock switching is disabled, Fail-Safe Clock Monitor is disabled 01 = Clock switching is enabled, Fail-Safe Clock Monitor is disabled 00 = Clock switching is enabled, Fail-Safe Clock Monitor is enabled FOS< ...

  • Page 12

    ... TABLE 5-6: FOSC CONFIGURATION BITS DESCRIPTION FOR dsPIC30F2011/2012, dsPIC30F3010/3011/3012/3013/3014, dsPIC30F4013, dsPIC30F5015/5016, dsPIC30F6010A/6011A/6012A/6013A/6014A AND dsPIC30F6015 (CONTINUED) Bit Field Register FPR<4:0> FOSC Alternate Oscillator Mode (when FOS<2:0> = 011b) 1xxxx = Reserved (do not use) 0111x = Reserved (do not use) 01101 = Reserved (do not use) 01100 = ECIO – External clock. OSC2 pin is I/O 01011 = EC – ...

  • Page 13

    ... No Data RAM is reserved for Boot Segment 10 = Small-sized Boot RAM 01 = Medium-sized Boot RAM 00 = Large-sized Boot RAM © 2010 Microchip Technology Inc. Description [128 bytes of RAM are reserved for Boot Segment] [256 bytes of RAM are reserved for Boot Segment] [512 bytes of RAM are reserved for Boot Segment in dsPIC30F5011/5013, and ...

  • Page 14

    ... N) bytes in dsPIC30F6010A/6011A/6012A/ 6013A/6014A/6015] [(512 – N) bytes of Data EEPROM are reserved for Secure Segment in dsPIC30F5011/5013, (1024 – N) bytes in dsPIC30F6011A/6013A, and (2048 – N) bytes in dsPIC30F6010A/6012A/6014A/6015] where N = Number of bytes of Data EEPROM reserved for Boot Sector. © 2010 Microchip Technology Inc. ...

  • Page 15

    ... FBS, FSS, FGS Reserved (read as ‘1’, write as ‘1’) — All Unimplemented (read as ‘0’, write as ‘0’) © 2010 Microchip Technology Inc. Description [Secure Segment starts after BS and ends at 0x001FFF] [Secure Segment starts after BS and ends at 0x003FFF] [Secure Segment starts after BS and ends at 0x007FFF] ...

  • Page 16

    TABLE 5-8: dsPIC30F CONFIGURATION REGISTERS (FOR dsPIC30F2010, dsPIC30F4011/4012 AND dsPIC30F6010/ 6011/6012/6013/ 6014) Address Name Bit 15 Bit 14 Bit 13 0xF80000 FOSC FCKSM<1:0> — 0xF80002 FWDT FWDTEN — — 0xF80004 FBORPOR MCLREN — — 0xF80006 FBS — — Reserved 0xF80008 ...

  • Page 17

    ... TABLE 5-10: dsPIC30F CONFIGURATION REGISTERS (FOR dsPIC30F2011/2012, dsPIC30F3010/3011/3012/3013/3014, dsPIC30F4013 AND dsPIC30F5015/5016) Address Name Bit 15 Bit 14 Bit 13 0xF80000 FOSC FCKSM<1:0> — 0xF80002 FWDT FWDTEN — — 0xF80004 FBORPOR MCLREN — — 0xF80006 FBS — — Reserved 0xF80008 FSS — — Reserved 0xF8000A FGS — ...

  • Page 18

    ... Programming”). Configuration registers can only be programmed to a value of ‘0’. ERASEB is the only way to reprogram code-protect bits from ON (‘0’) to OFF (‘1’). FSS, or FGS are clear, the entire device must be erased before it can be reprogrammed. © 2010 Microchip Technology Inc. ...

  • Page 19

    ... MCLR to V user mode is next entered, the program that was stored using Enhanced ICSP will execute. FIGURE 5-5: CONFIGURATION BIT PROGRAMMING FLOW ConfigAddress = ConfigAddress + 2 © 2010 Microchip Technology Inc. . When normal IL Start ConfigAddress = 0xF80000 Send PROGC Command ...

  • Page 20

    ... Similarly, when saving a hexadecimal file, all data EEPROM information must be included. An option to not include the data EEPROM information can be provided. Microchip Technology Inc. believes that this feature is important for the benefit of the end customer. to that segment ...

  • Page 21

    ... Similarly, while saving a hexadecimal file, all configuration information must be included. An option to not include the configuration information can be provided. Microchip Technology Inc. feels strongly that this feature is important for the benefit of the end customer. 6.7 Unit ID The dsPIC30F devices contain 32 instructions of Unit ID ...

  • Page 22

    ... Programming Executive Processes Command MSB LSB P9b P10 P9a PGC = Input (Idle) PGD = Output Table 8-1. If the programming executive and start Host Clocks Out Response MSB LSB P11 PGC = Input PGD = Output © 2010 Microchip Technology Inc. ...

  • Page 23

    ... SPI port. If the value of this field is incorrect, the command will not be properly received by the programming executive. © 2010 Microchip Technology Inc. 8.3 Packed Data Format When 24-bit instruction words are transferred across the 16-bit SPI interface, they are packed to conserve ...

  • Page 24

    ... Erase rows of data EEPROM from specified address. 5 ms/row Erase rows of code memory from specified address. 300 ms Query if the code memory and data EEPROM are blank Query the programming executive software version. Table 5-2 Table 5-3 Description for device-specific information. for device-specific information. © 2010 Microchip Technology Inc. ...

  • Page 25

    ... Expected Response (2 words): 0x1000 0x0002 Note: This instruction is not required for programming, but is development purposes only. © 2010 Microchip Technology Inc. 8.5.2 READD COMMAND Opcode “QVER Reserved0 Reserved1 0 Field ...

  • Page 26

    ... Addr_LS D_1 D_2 ... D_16 Description 0x4 0x13 0x0 MSB of 24-bit destination address LS 16 bits of 24-bit destination address 16-bit data word 1 16-bit data word 2 16-bit data words 3 through 15 16-bit data word 16 Table 5-3 for data EEPROM size © 2010 Microchip Technology Inc. ...

  • Page 27

    ... After all data has been programmed to code memory, the programming executive verifies the programmed data against the data in the command. Expected Response (2 words): 0x1500 0x0002 Note: Refer to Table 5-2 for code memory size information. © 2010 Microchip Technology Inc. 8.5.6 PROGC COMMAND Opcode Reserved Field Opcode Length ...

  • Page 28

    ... EEPROM will contain 0xFF. Expected Response (2 words): 0x1800 0x0002 Note: The ERASED command cannot be used to erase the Configuration registers or device ID. Code-protect Configuration registers can only be erased with the ERASEB command, while the device ID is read-only Length Addr_MSB Addr_LS Description © 2010 Microchip Technology Inc. ...

  • Page 29

    ... Expected Response (2 words): 0x1900 0x0002 Note: The ERASEP command cannot be used to erase the Configuration registers or device ID. Code-protect Configuration registers can only be erased with the ERASEB command, while the device ID is read-only. © 2010 Microchip Technology Inc. 8.5.10 QBLANK COMMAND Opcode PSize Reserved Field ...

  • Page 30

    ... However, it can be used to verify whether the programming executive command that the programmer transmitted. © 2010 Microchip Technology Inc QE_Code ... Description 9-1). If the command is processed. Since the ...

  • Page 31

    ... If the verify of the programming for the PROGD, PROGP or PROGC command fails, the QE_Code is set to 0x1. For all other programming executive errors, the QE_Code is 0x2. © 2010 Microchip Technology Inc. TABLE 9-4: QE_Code FOR NON-QUERY COMMANDS QE_Code ...

  • Page 32

    ... 0x01C0 0x1000 dsPIC30F3011 0x01C1 0x1000 dsPIC30F3012 0x00C1 — dsPIC30F3013 0x00C3 — dsPIC30F3014 0x0160 — dsPIC30F4011 0x0101 — dsPIC30F4012 0x0100 — dsPIC30F4013 0x0141 — dsPIC30F5011 0x0080 — dsPIC30F5013 0x0081 — dsPIC30F5015 0x0200 0x1000 dsPIC30F5016 0x0201 0x1000 dsPIC30F6010 0x0188 — dsPIC30F6010A 0x0281 — ...

  • Page 33

    ... Refer to Table 10-1 for the actual revision IDs. © 2010 Microchip Technology Inc. Description Encodes the device ID. Encodes the process of the device (always read as 0x001). Encodes the major revision number of the device. 000000 = A 000001 = B 000010 = C Encodes the minor revision number of the device ...

  • Page 34

    ... SIX command. After the forced SIX is clocked in, ICSP operation resumes as normal (the next 24 clock cycles load the first instruction word to the CPU). See Figure 11-1 for details. instructions must be followed by a NOP instruction. © 2010 Microchip Technology Inc. ...

  • Page 35

    ... Execute Previous Instruction, CPU Held In Idle Fetch REGOUT Control Code PGD = Input © 2010 Microchip Technology Inc. The REGOUT instruction is unique because the PGD pin is an input when the control code is transmitted to the device. However, once the control code is processed, the PGD pin becomes an output as the VISI register is shifted out ...

  • Page 36

    ... Reset vector). 3: Before leaving the Reset vector, execute two GOTO instructions, followed by a single NOP instruction must be executed. FIGURE 11-4: ENTERING ICSP™ MODE IHH MCLR PGD PGC DS70102K-page 36 Figure 11- 10 μ Execute 2 NOP instructions © 2010 Microchip Technology Inc. ...

  • Page 37

    ... Erase all Data EEPROM allocated to Secure Segment. 0x404E Erase General Segment, then erase FGS configuration register. 0x4046 Erase all Data EEPROM allocated to General Segment. © 2010 Microchip Technology Inc. TABLE 11-3: NVMCON described in Value through 0x4008 0x4005 Section 11.13 ...

  • Page 38

    ... Steps 2-8 are only required for the dsPIC30F5011/5013 devices. These steps may be skipped for all other devices in the dsPIC30F family. DS70102K-page 38 11-2). Description (1) #0x4008, W10 W10, NVMCON #0xF8, W0 W0, TBLPAG #0x6, W7 (1) W6 (1) #0x55, W8 #0xAA, W9 W8, NVMKEY W9, NVMKEY (1) #0x407F, W10 W10, NVMCON (1) (1) (1) © 2010 Microchip Technology Inc. ...

  • Page 39

    ... NOP Note 1: Steps 2-8 are only required for the dsPIC30F5011/5013 devices. These steps may be skipped for all other devices in the dsPIC30F family. © 2010 Microchip Technology Inc. Description #0x55, W8 W8, NVMKEY #0xAA, W9 W9, NVMKEY Section 13.0 “AC/DC Characteristics and Requirements” ...

  • Page 40

    ... Note: Program memory must be erased before writing any data to program memory. Description W6 W6, NVMADR W6, NVMADRU #0x40, W7 #0x4071, W10 W10, NVMCON #0x55, W8 W8, NVMKEY #0xAA, W9 W9, NVMKEY Section 13.0 “AC/DC Characteristics and Requirements”) Table 11-5. However, © 2010 Microchip Technology Inc. ...

  • Page 41

    ... MOV 0000 883B16 MOV 0000 200207 MOV Step 17: Set NVMCON to erase 1 row of data memory. 0000 24075A MOV 0000 883B0A MOV © 2010 Microchip Technology Inc. Description W6, W7, W6 SR, #C NVMADRU W6, NVMADR W6 W6, NVMADR #0x80, W7 W7, NVMADRU #0x40, W7 #0x4071, W10 W10, NVMCON #0x55, W8 ...

  • Page 42

    ... GOTO 0x100 0000 000000 NOP Step 22: Repeat Steps 17-21 until all rows of data memory are erased. DS70102K-page 42 Description #0x55, W8 W8, NVMKEY #0xAA, W9 W9, NVMKEY Section 13.0 “AC/DC Characteristics and Requirements”) W6, W7, W6 W6, NVMADR © 2010 Microchip Technology Inc. ...

  • Page 43

    ... MOV 0000 000000 NOP © 2010 Microchip Technology Inc. tion register. In Step 4, the TBLPAG register is initialized, to 0xF8, for writing to the Configuration registers. In Step 5, the value to write to the each Configuration register (0xFFFF) is loaded to W6. In Step 6, the Configuration register data is written to the write latch using the TBLWTL instruction ...

  • Page 44

    ... Step 9: Reset device internal PC. 0000 040100 GOTO 0x100 0000 000000 NOP Step 10: Repeat steps 3-9 until all 7 Configuration registers are cleared. DS70102K-page 44 Description #0x55, W8 W8, NVMKEY #0xAA, W9 W9, NVMKEY Section 13.0 “AC/DC Characteristics and Requirements”) © 2010 Microchip Technology Inc. ...

  • Page 45

    ... MOV 0000 2xxxx5 MOV © 2010 Microchip Technology Inc. In Step 5, eight TBLWT instructions are used to copy the data from W0:W5 to the write latches of code memory. Since code memory is programmed 32 instruction words at a time, Steps 4 and 5 are repeated eight times to load all the write latches (Step 6). ...

  • Page 46

    ... NOP Step 10: Repeat steps 2-9 until all code memory is programmed. DS70102K-page 46 Description W6 [W6++], [W7] [W6++], [W7++] [W6++], [++W7] [W6++], [W7++] [W6++], [W7] [W6++], [W7++] [W6++], [++W7] [W6++], [W7++] #0x55, W8 W8, NVMKEY #0xAA, W9 W9, NVMKEY NVMCON, #WR Section 13.0 “AC/DC Characteristics and Requirements”) NVMCON, #WR © 2010 Microchip Technology Inc. ...

  • Page 47

    ... NOP 0000 000000 NOP Step 6: Repeat steps 4-5 four times to load the write latches for 16 data words. © 2010 Microchip Technology Inc. during each operation, only working registers W0:W3 are used as temporary holding registers for the data to be programmed. Table 11-9 shows the ICSP programming details for writing data EEPROM ...

  • Page 48

    ... NOP Step 9: Reset device internal PC. 0000 040100 GOTO 0x100 0000 000000 NOP Step 10: Repeat steps 2-9 until all data memory is programmed. DS70102K-page 48 Description #0x55, W8 W8, NVMKEY #0xAA, W9 W9, NVMKEY Section 13.0 “AC/DC Characteristics and Requirements”) © 2010 Microchip Technology Inc. ...

  • Page 49

    ... NOP 0000 000000 NOP © 2010 Microchip Technology Inc. To minimize the reading time, the packed instruction word format that was utilized for writing is also used for reading (see Figure W7 is initialized, and four instruction words are read from code memory and stored to working registers W0:W5 ...

  • Page 50

    ... Clock out contents of VISI register 0000 000000 NOP Step 5: Reset the device internal PC. 0000 040100 GOTO 0x100 0000 000000 NOP Step 6: Repeat steps 3-5 until all desired code memory is read. DS70102K-page 50 Description W0, VISI W1, VISI W2, VISI W3, VISI W4, VISI W5, VISI © 2010 Microchip Technology Inc. ...

  • Page 51

    ... NOP Step 6: Repeat steps 3-5 six times to read all of configuration memory. © 2010 Microchip Technology Inc. Table 11-11 shows the ICSP programming details for reading all of the configuration memory. Note that the TBLPAG register is hard-coded to 0xF8 (the upper byte address of configuration memory), and the read pointer W6 is initialized to 0x0000 ...

  • Page 52

    ... DS70102K-page 52 Table 11-12 shows the ICSP programming details for reading data memory. Note that the TBLPAG register is hard-coded to 0x7F (the upper byte address of all locations of data memory). Description #0x7F, W0 W0, TBLPAG #<SourceAddress15:0> W0, VISI W1, VISI W2, VISI W3, VISI © 2010 Microchip Technology Inc. ...

  • Page 53

    ... Clock out contents of the VISI register 0000 000000 NOP © 2010 Microchip Technology Inc. 11.14 Exiting ICSP Mode After confirming that the programming executive is resident in memory, or loading the programming executive, ICSP mode is exited by removing power to the device or bringing MCLR to V then take place by following the procedure outlined in Section 5.0 “ ...

  • Page 54

    ... This control flow is summarized in Table Description #0x4072, W10 W10, NVMCON #0x55, W8 W8, NVMKEY #0xAA, W9 W9, NVMKEY Section 13.0 “AC/DC Characteristics and Requirements”) #0x80, W0 W0, TBLPAG W7 #0x4001, W10 W10, NVMCON #<LSW0>, W0 #<MSB1:MSB0>, W1 #<LSW1>, W2 #<LSW2>, W3 #<MSB3:MSB2>, W4 #<LSW3>, W5 12-1. © 2010 Microchip Technology Inc. ...

  • Page 55

    ... NOP Step 12: Reset the device internal PC. 0000 040100 GOTO 0x100 0000 000000 NOP Step 13: Repeat Steps 7-12 until all 23 rows of executive memory are programmed. © 2010 Microchip Technology Inc. Description W6 [W6++], [W7] [W6++], [W7++] [W6++], [++W7] [W6++], [W7++] [W6++], [W7] [W6++], [W7++] [W6++], [++W7] [W6++], [W7++] ...

  • Page 56

    ... Table 12-2. Note that in Step 2, the TBLPAG register is set to 0x80 such that executive memory may be read. Description #0x80, W0 W0, TBLPAG W6 W7 [W6], [W7++] [W6++], [W7++] [++W6], [W7++] [W6++], [W7++] [W6], [W7++] [W6++], [W7++] [++W6], [W7++] [W6++], [W7] “Reading Code Memory”. A © 2010 Microchip Technology Inc. ...

  • Page 57

    ... Clock out contents of VISI register Step 5: Reset the device internal PC. 0000 040100 GOTO 0x100 0000 000000 NOP Step 6: Repeat Steps 3-5 until all 736 instruction words of executive memory are read. © 2010 Microchip Technology Inc. Description W0, VISI W1, VISI W2, VISI W3, VISI W4, VISI W5, VISI DS70102K-page 57 ...

  • Page 58

    ... PP ↑ 2 — — 20 — 10 — © 2010 Microchip Technology Inc. Units Conditions V — μA — mA Row Erase Program memory mA Row Erase Data EEPROM mA Bulk Erase V — V — V — V — 8 ...

  • Page 59

    ... PROG P12b T Row Programming cycle time PROG P13a T Bulk/Row Erase cycle time ERA P13b T Bulk/Row Erase cycle time ERA © 2010 Microchip Technology Inc. Standard Operating Conditions (unless otherwise stated) Operating Temperature: 25° recommended Min Max Units μs 15 — 5 — μs μ ...

  • Page 60

    ... Disabled Enabled dsPIC30F3013 Disabled Enabled dsPIC30F3014 Disabled Enabled dsPIC30F4011 Disabled Enabled dsPIC30F4012 Disabled Enabled dsPIC30F4013 Disabled Enabled dsPIC30F5011 Disabled Enabled dsPIC30F5013 Disabled Enabled dsPIC30F5015 Disabled Enabled Item Description: SUM(a:b) = Byte sum of locations inclusive (all 3 bytes of code memory) CFGB = Configuration Block (masked) = Byte sum of ((FOSC&0xC10F) + (FWDT&0x803F) + (FBORPOR& ...

  • Page 61

    ... Disabled Enabled Item Description: SUM(a:b) = Byte sum of locations inclusive (all 3 bytes of code memory) CFGB = Configuration Block (masked) = Byte sum of ((FOSC&0xC10F) + (FWDT&0x803F) + (FBORPOR&0x87B3) + (FBS&0x310F) + (FSS&0x330F) + (FGS&0x0007) + (FICD&0xC003)) © 2010 Microchip Technology Inc. Checksum Computation CFGB+SUM(0:00AFFF) CFGB CFGB+SUM(0:017FFF) CFGB CFGB+SUM(0:017FFF) CFGB CFGB+SUM(0:015FFF) ...

  • Page 62

    ... Notice that the data record (line 2) has a load address of 0200, while the source code specified address 0x100. Note also that the data is represented in “little- endian” format, meaning the Least Significant Byte (LSB) appears first. The phantom byte appears last, just before the checksum. © 2010 Microchip Technology Inc. ...

  • Page 63

    ... Updated Steps 4 and 11 in Table 12-1: Programming the Programming Executive • Renamed parameters: P12 to P12a and P13 to P13a, and added parameters P12b and P13b in Table 13-1: AC/DC Characteristics © 2010 Microchip Technology Inc. 10-2: 11-5: Serial Serial Serial Serial Figure 11-4) ...

  • Page 64

    ... NOTES: DS70102K-page 64 © 2010 Microchip Technology Inc. ...

  • Page 65

    ... PICtail, REAL ICE, rfLAB, Select Mode, Total Endurance, TSHARC, UniWinDriver, WiperLock and ZENA are trademarks of Microchip Technology Incorporated in the U.S.A. and other countries. SQTP is a service mark of Microchip Technology Incorporated in the U.S.A. All other trademarks mentioned herein are property of their respective companies. ...

  • Page 66

    ... Philippines - Manila Tel: 63-2-634-9065 Fax: 63-2-634-9069 Singapore Tel: 65-6334-8870 Fax: 65-6334-8850 Taiwan - Hsin Chu Tel: 886-3-6578-300 Fax: 886-3-6578-370 Taiwan - Kaohsiung Tel: 886-7-213-7830 Fax: 886-7-330-9305 Taiwan - Taipei Tel: 886-2-2500-6610 Fax: 886-2-2508-0102 Thailand - Bangkok Tel: 66-2-694-1351 Fax: 66-2-694-1350 © 2010 Microchip Technology Inc. 08/04/10 ...