DSPIC30F5011-20I/PTG Microchip Technology, DSPIC30F5011-20I/PTG Datasheet
DSPIC30F5011-20I/PTG
Specifications of DSPIC30F5011-20I/PTG
Related parts for DSPIC30F5011-20I/PTG
DSPIC30F5011-20I/PTG Summary of contents
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... Microchip Technology Inc. dsPIC30F5011/5013 Data Sheet High-Performance, 16-bit Digital Signal Controllers DS70116H ...
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... PowerMate, PowerTool, REAL ICE, rfLAB, Select Mode, Total Endurance, UNI/O, WiperLock and ZENA are trademarks of Microchip Technology Incorporated in the U.S.A. and other countries. SQTP is a service mark of Microchip Technology Incorporated in the U.S.A. All other trademarks mentioned herein are property of their respective companies. ...
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... All DSP instructions are single cycle - Multiply-Accumulate (MAC) operation • Single cycle ±16 shift © 2008 Microchip Technology Inc. dsPIC30F5011/5013 Peripheral Features: • High-current sink/source I/O pins: 25 mA/25 mA • Five 16-bit timers/counters; optionally pair up 16-bit timers into 32-bit timer modules • ...
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... CMOS Technology: • Low-power, high-speed Flash technology • Wide operating voltage range (2.5V to 5.5V) • Industrial and Extended temperature ranges • Low power consumption dsPIC30F5011/5013 Controller Family Program Memory Device Pins Bytes Instructions dsPIC30F5011 64 66K 22K dsPIC30F5013 80 66K 22K DS70116H-page 4 ...
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... AN3/CN5/RB3 13 AN2/SS1/LVDIN/CN4/RB2 14 AN1/V -/CN3/RB1 15 REF AN0/V +/CN2/RB0 16 REF Note: For descriptions of individual pins, see Section 1.0 “Device Overview”. © 2008 Microchip Technology Inc. dsPIC30F5011/5013 48 EMUC1/SOSCO/T1CK/CN0/RC14 47 EMUD1/SOSCI/T4CK/CN1/RC13 46 EMUC2/OC1/RD0 45 IC4/INT4/RD11 44 IC3/INT3/RD10 43 IC2/INT2/RD9 42 IC1/INT1/RD8 dsPIC30F5011 40 OSC2/CLKO/RC15 39 OSC1/CLKI SCL/RG2 36 SDA/RG3 35 EMUC3/SCK1/INT0/RF6 34 U1RX/SDI1/RF2 33 EMUD3/U1TX/SDO1/RF3 DS70116H-page 5 ...
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... Pin Diagrams (Continued) 80-Pin TQFP 1 COFS/RG15 T2CK/RC1 2 3 T3CK/RC2 4 T4CK/RC3 T5CK/RC4 5 SCK2/CN8/RG6 6 SDI2/CN9/RG7 7 SDO2/CN10/RG8 8 MCLR 9 SS2/CN11/RG9 INT1/RA12 13 INT2/RA13 14 AN5/CN7/RB5 15 AN4/CN6/RB4 16 AN3/CN5/RB3 17 AN2/SS1/LVDIN/CN4/RB2 18 PGC/EMUC/AN1/CN3/RB1 19 PGD/EMUD/AN0/CN2/RB0 20 Note: For descriptions of individual pins, see Section 1.0 “Device Overview”. DS70116H-page dsPIC30F5013 EMUC1/SOSCO/T1CK/CN0/RC14 EMUD1/SOSCI/CN1/RC13 EMUC2/OC1/RD0 ...
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... When contacting a sales office, please specify which device, revision of silicon and data sheet (include literature number) you are using. Customer Notification System Register on our web site at www.microchip.com to receive the most current information on all of our products. © 2008 Microchip Technology Inc. dsPIC30F5011/5013 DS70116H-page 7 ...
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... NOTES: DS70116H-page 8 © 2008 Microchip Technology Inc. ...
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... Digital Signal Controller (DSC) devices. The dsPIC30F5011/5013 devices contain extensive Digital Signal Processor (DSP) functionality within a high-performance 16-bit microcontroller (MCU) architecture. Figure 1-1 and Figure 1-2 show device block diagrams for dsPIC30F5011 and dsPIC30F5013, respectively. © 2008 Microchip Technology Inc. dsPIC30F5011/5013 DS70116H-page 9 ...
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... FIGURE 1-1: dsPIC30F5011 BLOCK DIAGRAM Y Data Bus Interrupt PSV & Table Controller Data Access 8 24 Control Block 24 24 PCU Program Counter Stack Address Latch Control Logic Program Memory (66 Kbytes) Data EEPROM (1 Kbyte) 16 Data Latch ROM Latch 24 16 Instruction Decode & ...
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... Oscillator OSC1/CLKI Generation Start-up Timer POR/BOR Reset Watchdog MCLR Timer Low-Voltage Detect CAN1, 12-bit ADC CAN2 Timers © 2008 Microchip Technology Inc. dsPIC30F5011/5013 X Data Bus Data Latch Data Latch Y Data X Data 16 RAM RAM (2 Kbytes) (2 Kbytes) 16 Address Address Latch Latch RAGU Y AGU ...
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... Table 1-1 provides a brief description of device I/O pinouts and the functions that may be multiplexed to a port pin. Multiple functions may exist on one port pin. When multiplexing occurs, the peripheral module’s functional requirements may force an override of the data direction of the port pin. ...
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... I REF Legend: CMOS = CMOS compatible input or output ST = Schmitt Trigger input with CMOS levels I = Input © 2008 Microchip Technology Inc. dsPIC30F5011/5013 Buffer Type ST/CMOS Oscillator crystal input. ST buffer when configured in RC mode; CMOS otherwise. — Oscillator crystal output. Connects to crystal or resonator in Crystal Oscillator mode. Optionally functions as CLKO in RC and EC modes ...
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... NOTES: DS70116H-page 14 © 2008 Microchip Technology Inc. ...
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... Each data word consists of 2 bytes, and most instructions can address data either as words or bytes. © 2008 Microchip Technology Inc. dsPIC30F5011/5013 There are two methods of accessing data stored in program memory: • The upper 32 Kbytes of data space memory can ...
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... The core does not support a multi-stage instruction pipeline. However, a single stage instruction prefetch mechanism is used, which accesses and partially decodes instructions a cycle ahead of execution, in order to maximize available execution time. Most instructions execute in a single cycle with certain exceptions. The core features a vectored exception processing structure for traps and interrupts, with 62 independent vectors ...
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... DSP AccA Accumulators AccB PC22 0 7 TABPAG TBLPAG Data Table Page Address 7 0 PSVPAG PSVPAG OAB SAB DA SRH © 2008 Microchip Technology Inc. dsPIC30F5011/5013 D15 D0 W0/WREG W10 W11 W12/DSP Offset W13/DSP Write Back W14/Frame Pointer W15/Stack Pointer SPLIM AD15 AD31 PC0 0 ...
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... Divide Support The dsPIC DSC devices feature a 16/16-bit signed fractional divide operation, as well as 32/16-bit and 16/16-bit signed and unsigned operations, in the form of single instruction iterative divides. The following instructions and data sizes are supported: 1. DIVF - 16/16 signed fractional divide 2 ...
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... MAC MOVSAC MPY MPY.N MSC © 2008 Microchip Technology Inc. dsPIC30F5011/5013 The DSP engine has various options selected through various bits in the CPU Core Configuration register (CORCON), as listed below: • Fractional or integer DSP multiply (IF) • Signed or unsigned DSP multiply (US) • Conventional or convergent rounding (RND) • ...
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... FIGURE 2-2: DSP ENGINE BLOCK DIAGRAM 40 Carry/Borrow Out Carry/Borrow In DS70116H-page 20 40-bit Accumulator A 40-bit Accumulator B Saturate Adder Negate Barrel 16 Shifter 40 Sign-Extend 17-bit Multiplier/Scaler 16 16 To/From W Array Round u Logic Zero Backfill © 2008 Microchip Technology Inc. ...
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... For the ADD and LAC instructions, the data to be accumulated or loaded can be optionally scaled via the barrel shifter, prior to accumulation. © 2008 Microchip Technology Inc. dsPIC30F5011/5013 2.4.2.1 Adder/Subtracter, Overflow and Saturation The adder/subtracter is a 40-bit adder with an optional zero input into one side and either true, or complement data into the other input ...
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... The SA and SB bits are modified each time data passes through the adder/subtracter but can only be cleared by the user. When set, they indicate that the accumulator has overflowed its maximum range (bit 31 for 32-bit saturation, or bit 39 for 40-bit saturation) and will be saturated (if saturation is enabled). When satu- ...
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... If the SATDW bit in the CORCON register is not set, the input data is always passed through unmodified under all conditions. © 2008 Microchip Technology Inc. dsPIC30F5011/5013 2.4.3 BARREL SHIFTER The barrel shifter is capable of performing up to 16-bit arithmetic or logic right shifts 16-bit left shifts in a single cycle ...
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... NOTES: DS70116H-page 24 © 2008 Microchip Technology Inc. ...
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... In Table 3-1, Program Space Address Construction, bit 23 allows access to the Device ID, the User ID and the Configuration bits. Otherwise, bit 23 is always clear. © 2008 Microchip Technology Inc. dsPIC30F5011/5013 FIGURE 3-1: PROGRAM SPACE MEMORY MAP Reset - GOTO Instruction Reset - Target Address ...
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... TABLE 3-1: PROGRAM SPACE ADDRESS CONSTRUCTION Access Access Type Space Instruction Access User User TBLRD/TBLWT (TBLPAG<7> Configuration TBLRD/TBLWT (TBLPAG<7> Program Space Visibility User FIGURE 3-2: DATA ACCESS FROM PROGRAM SPACE ADDRESS GENERATION Using Program 0 Counter Using Program 0 Space Visibility Using ...
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... Program Memory ‘Phantom’ Byte (read as ‘0’) © 2008 Microchip Technology Inc. dsPIC30F5011/5013 A set of table instructions are provided to move byte or word sized data to and from program space. 1. TBLRDL: Table Read Low Word: Read the lsw of the program address; ...
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... FIGURE 3-4: PROGRAM DATA TABLE ACCESS (MOST SIGNIFICANT BYTE) PC Address 0x000000 00000000 0x000002 00000000 00000000 0x000004 0x000006 00000000 Program Memory ‘Phantom’ Byte (read as ‘0’) 3.1.2 DATA ACCESS FROM PROGRAM MEMORY USING PROGRAM SPACE VISIBILITY The upper 32 Kbytes of data space may optionally be mapped into any 16K word program space page ...
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... The core has two data spaces. The data spaces can be considered either separate (for instructions one unified linear address range (for MCU instructions). The data spaces are accessed using two Address Generation Units (AGUs) and separate data paths. © 2008 Microchip Technology Inc. dsPIC30F5011/5013 0x0000 (1) PSVPAG 0x01 8 0x8000 23 Address Concatenation ...
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... When executing any instruction other than one of the MAC class of instructions, the X block consists of the 64-Kbyte data address space (including all Y addresses). When executing one of the MAC class of instructions, the X block consists of the 64 Kbyte data address space excluding the Y address block (for data reads only) ...
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... DATA SPACE FOR MCU AND DSP (MAC CLASS) INSTRUCTIONS EXAMPLE SFR SPACE (Y SPACE) Non-MAC Class Ops (Read/Write) MAC Class Ops (Write) Indirect EA using any W © 2008 Microchip Technology Inc. dsPIC30F5011/5013 SFR SPACE UNUSED Y SPACE UNUSED UNUSED MAC Class Ops (Read) Indirect EA using W8, W9 ...
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... DATA SPACES X data space is used by all instructions and supports all Addressing modes. There are separate read and write data buses. The X read data bus is the return data path for all instructions that view data space as combined X and Y address space also the X address space data path for the dual operand read instructions (MAC class) ...
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... POP : [--W15] PUSH : [W15++] 3.2.7 DATA RAM PROTECTION FEATURE The dsPIC30F5011/5013 devices support data RAM protection features which enable segments of RAM to be protected when used in conjunction with Boot and Secure Code Segment Security. BSRAM (Secure RAM segment for BS) is accessible only from the Boot Segment Flash code when enabled ...
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TABLE 3-3: CORE REGISTER MAP Address SFR Name Bit 15 Bit 14 Bit 13 Bit 12 (Home) W0 0000 W1 0002 W2 0004 W3 0006 W4 0008 W5 000A W6 000C W7 000E W8 0010 W9 0012 W10 0014 ...
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TABLE 3-3: CORE REGISTER MAP (CONTINUED) Address SFR Name Bit 15 Bit 14 Bit 13 Bit 12 (Home) CORCON 0044 — — — US MODCON 0046 XMODEN YMODEN — — XMODSRT 0048 XMODEND 004A YMODSRT 004C YMODEND 004E XBREV ...
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... NOTES: DS70116H-page 36 © 2008 Microchip Technology Inc. ...
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... The INTCON2 register controls the external interrupt request signal behavior and the use of the alternate vector table. © 2008 Microchip Technology Inc. dsPIC30F5011/5013 • INTTREG<15:0> The associated interrupt vector number and the new CPU interrupt priority level are latched into vector number (VECNUM<5:0>) and interrupt level (ILR< ...
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... Interrupt Priority The user-assignable interrupt priority (IP<2:0>) bits for each individual interrupt source are located in the Least Significant 3 bits of each nibble within the IPCx register(s). Bit 3 of each nibble is not used and is read as a ‘0’. These bits define the priority level assigned to a particular interrupt by the user ...
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... Trap Lockout: Occurrence of multiple trap conditions simultaneously will cause a Reset. © 2008 Microchip Technology Inc. dsPIC30F5011/5013 4.3 Traps Traps can be considered as non-maskable interrupts indicating a software or hardware error, which adhere to a predefined priority as shown in Figure 4-1. They ...
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... Address Error Trap: This trap is initiated when any of the following circumstances occurs: • A misaligned data word access is attempted. • A data fetch from an unimplemented data memory location is attempted. • A data access of an unimplemented program memory location is attempted. • An instruction fetch from vector space is attempted ...
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... The RETFIE (return from interrupt) instruction will unstack the program counter and STATUS registers to return the processor to its state prior to the interrupt sequence. © 2008 Microchip Technology Inc. dsPIC30F5011/5013 4.5 Alternate Vector Table In program memory, the Interrupt Vector Table (IVT) is followed by the Alternate Interrupt Vector Table (AIVT), as shown in Figure 4-1 ...
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TABLE 4-2: INTERRUPT CONTROLLER REGISTER MAP SFR ADR Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Name INTCON1 0080 NSTDIS — — — — INTCON2 0082 ALTIVT DISI — — — IFS0 0084 CNIF MI2CIF SI2CIF NVMIF ADIF ...
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... Register Indirect Pre-modified Register Indirect with Register Offset The sum of Wn and Wb forms the EA. Register Indirect with Literal Offset © 2008 Microchip Technology Inc. dsPIC30F5011/5013 5.1.1 FILE REGISTER INSTRUCTIONS Most file register instructions use a 13-bit address field (f) to directly address data present in the first 8192 bytes of data memory (near data space) ...
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... MOVE AND ACCUMULATOR INSTRUCTIONS Move instructions and the DSP accumulator class of instructions provide a greater degree of addressing flexibility than other instructions. In addition to the addressing modes supported by most MCU instructions, move and accumulator instructions also support Register Indirect with Register Offset Addressing mode, also referred to as Register Indexed mode ...
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... Address 0x1100 0x1163 Start Addr = 0x1100 End Addr = 0x1163 Length = 0x0032 words © 2008 Microchip Technology Inc. dsPIC30F5011/5013 5.2.2 W ADDRESS REGISTER SELECTION The Modulo and Bit-Reversed Addressing Control registers: register MODCON<15:0> contains enable flags as well register field to specify the W address registers. ...
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... MODULO ADDRESSING APPLICABILITY Modulo addressing can be applied to the Effective Address (EA) calculation associated with any W register important to realize that the address boundaries check for addresses less than, or greater than, the upper (for incrementing buffers), and lower (for decrementing buffers) boundary (not just equal to) ...
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... TABLE 5-2: BIT-REVERSED ADDRESS SEQUENCE (16-ENTRY) Normal Address TABLE 5-3: BIT-REVERSED ADDRESS MODIFIER VALUES FOR XBREV REGISTER Buffer Size (Words) 2048 1024 512 256 128 © 2008 Microchip Technology Inc. dsPIC30F5011/5013 Bit-Reversed Address Decimal XB<14:0> Bit-Reversed Address Modifier Value A0 Decimal 0x0400 ...
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... NOTES: DS70116H-page 48 © 2008 Microchip Technology Inc. ...
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... Addressing Using Table Instruction User/Configuration Space Select © 2008 Microchip Technology Inc. dsPIC30F5011/5013 6.2 Run-Time Self-Programming (RTSP) RTSP is accomplished using TBLRD (table read) and TBLWT (table write) instructions. With RTSP, the user may erase program memory, 32 instructions (96 bytes time and can write program memory data, 32 instructions (96 bytes time ...
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... RTSP Operation The dsPIC30F Flash program memory is organized into rows and panels. Each row consists of 32 instructions bytes. Each panel consists of 128 rows instructions. RTSP allows the user to erase one row (32 instructions time and to program four instructions at one time. RTSP may be ...
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... MOV #0xAA,W1 MOV W1 NVMKEY , BSET NVMCON,#WR NOP NOP © 2008 Microchip Technology Inc. dsPIC30F5011/5013 4. Write 32 instruction words of data from data RAM “image” into the program Flash write latches. 5. Program 32 instruction words into program Flash. a) Set up NVMCON register for multi-word, the ...
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... LOADING WRITE LATCHES Example 6-2 shows a sequence of instructions that can be used to load the 96 bytes of write latches. 32 TBLWTL and 32 TBLWTH instructions are needed to load the write latches selected by the table pointer. EXAMPLE 6-2: LOADING WRITE LATCHES ; Set up a pointer to the first program memory location to be written ...
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TABLE 6-1: NVM REGISTER MAP File Name Addr. Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 NVMCON 0760 WR WREN WRERR NVMADR 0762 NVMADRU 0764 — — — NVMKEY 0766 — — — ...
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... NOTES: DS70116H-page 54 © 2008 Microchip Technology Inc. ...
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... The write typically requires complete but the write time will vary with voltage and temperature. © 2008 Microchip Technology Inc. dsPIC30F5011/5013 A program or erase operation on the data EEPROM does not stop the instruction flow. The user is responsible for waiting for the appropriate duration of ...
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... Erasing Data EEPROM 7.2.1 ERASING A BLOCK OF DATA EEPROM In order to erase a block of data EEPROM, the NVMADRU and NVMADR registers must initially point to the block of memory to be erased. Configure NVMCON for erasing a block of data EEPROM, and set the ERASE and WREN bits in the NVMCON register ...
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... Write cycle will complete in 2mS. CPU is not stalled for the Data Write Cycle ; User can poll WR bit, use NVMIF or Timer IRQ to determine write complete © 2008 Microchip Technology Inc. dsPIC30F5011/5013 The write will not initiate if the above sequence is not exactly followed (write 0x55 to NVMKEY, write 0xAA to NVMCON, then set WR bit) for each word ...
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... WRITING A BLOCK OF DATA EEPROM To write a block of data EEPROM, write to all sixteen latches first, then set the NVMCON register and program the block. EXAMPLE 7-5: DATA EEPROM BLOCK WRITE MOV #LOW_ADDR_WORD,W0 MOV #HIGH_ADDR_WORD,W1 MOV W1 TBLPAG , MOV #data1,W2 TBLWTL W2 [ W0]++ , MOV ...
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... This should be used in applications where excessive writes can stress bits near the specification limit. © 2008 Microchip Technology Inc. dsPIC30F5011/5013 7.5 Protection Against Spurious Write There are conditions when the device may not want to write to the data EEPROM memory ...
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... NOTES: DS70116H-page 60 © 2008 Microchip Technology Inc. ...
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... WR Port Read LAT Read Port © 2008 Microchip Technology Inc. dsPIC30F5011/5013 Any bit and its associated data and control registers that are not valid for a particular device will be disabled. That means the corresponding LATx and TRISx registers and the port pin will read as zeros. ...
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... FIGURE 8-2: BLOCK DIAGRAM OF A SHARED PORT STRUCTURE Peripheral Module Peripheral Input Data Peripheral Module Enable Peripheral Output Enable Peripheral Output Data PIO Module Read TRIS Data Bus WR TRIS TRIS Latch WR LAT + WR Port Data Latch Read LAT Read Port 8.2 ...
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... LATA14 LATA13 LATA12 Legend: — = unimplemented, read as ‘0’ Note 1: Refer to “dsPIC30F Family Reference Manual” (DS70046) for descriptions of register bit fields. 2: PORTA is not implemented in dsPIC30F5011 devices. TABLE 8-2: PORTB REGISTER MAP FOR dsPIC30F5011/5013 SFR Addr. Bit 15 Bit 14 Bit 13 Bit 12 Name ...
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... RD13 RD12 LATD 02D6 LATD15 LATD14 LATD13 LATD12 LATD11 Note 1: Refer to “dsPIC30F Family Reference Manual” (DS70046) for descriptions of register bit fields. TABLE 8-7: PORTF REGISTER MAP FOR dsPIC30F5011 SFR Addr. Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Name TRISF 02DE — — ...
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... Legend: — = unimplemented, read as ‘0’ Note 1: Refer to “dsPIC30F Family Reference Manual” (DS70046) for descriptions of register bit fields. TABLE 8-9: PORTG REGISTER MAP FOR dsPIC30F5011/5013 SFR Addr. Bit 15 Bit 14 Bit 13 Bit 12 Name TRISG 02E4 TRISG15 TRISG14 TRISG13 TRISG12 ...
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... Legend: — = unimplemented, read as ‘0’ Note 1: Refer to “dsPIC30F Family Reference Manual” (DS70046) for descriptions of register bit fields. TABLE 8-11: INPUT CHANGE NOTIFICATION REGISTER MAP FOR dsPIC30F5011 (BITS 7-0) SFR Addr. Bit 7 Bit 6 Name CNEN1 00C0 CN7IE ...
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... SOSCO/ T1CK LPOSCEN SOSCI © 2008 Microchip Technology Inc. dsPIC30F5011/5013 These operating modes are determined by setting the appropriate bit(s) in the 16-bit SFR, T1CON. Figure 9-1 presents a block diagram of the 16-bit timer module. 16-bit Timer Mode: In the 16-bit Timer mode, the timer ...
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... Timer Gate Operation The 16-bit timer can be placed in the Gated Time Accumulation mode. This mode allows the internal T to increment the respective timer when the gate input signal (T1CK pin) is asserted high. Control bit TGATE (T1CON<6>) must be set to enable this mode. The timer must be enabled (TON = 1) and the timer clock source set to internal (TCS = 0) ...
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... The TSIDL bit should be cleared to ‘0’ in order for RTC to continue operation in Idle mode. © 2008 Microchip Technology Inc. dsPIC30F5011/5013 9.5.2 RTC INTERRUPTS When an interrupt event occurs, the respective interrupt flag, T1IF, is asserted and an interrupt will be generated if enabled ...
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TABLE 9-1: TIMER1 REGISTER MAP SFR Name Addr. Bit 15 Bit 14 Bit 13 Bit 12 TMR1 0100 PR1 0102 T1CON 0104 TON — TSIDL — Legend uninitialized bit; — = unimplemented, read as ‘0’ Note 1: ...
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... Interrupt on a 32-bit period register match These operating modes are determined by setting the appropriate bit(s) in the 16-bit T2CON and T3CON SFRs. © 2008 Microchip Technology Inc. dsPIC30F5011/5013 For 32-bit timer/counter operation, Timer2 is the least significant word and Timer3 is the most significant word of the 32-bit timer. Note: For 32-bit timer operation, T3CON control bits are ignored ...
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... FIGURE 10-1: 32-BIT TIMER2/3 BLOCK DIAGRAM Data Bus<15:0> TMR3HLD Write TMR2 Read TMR2 16 Reset ADC Event Trigger Equal 0 T3IF Event Flag 1 TGATE (T2CON<6>) T2CK Note: Timer Configuration bit T32 (T2CON<3>) must be set to ‘ bits are respective to the T2CON register. DS70116H-page 72 ...
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... Reset 0 T2IF Event Flag 1 TGATE T2CK FIGURE 10-3: 16-BIT TIMER3 BLOCK DIAGRAM ADC Event Trigger Equal Reset 0 T3IF Event Flag 1 TGATE T3CK © 2008 Microchip Technology Inc. dsPIC30F5011/5013 PR2 Comparator x 16 TMR2 TGATE TON 1 x Gate Sync PR3 Comparator x 16 TMR3 ...
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... Timer Gate Operation The 32-bit timer can be placed in the Gated Time Accumulation mode. This mode allows the internal T to increment the respective timer when the gate input signal (T2CK pin) is asserted high. Control bit TGATE (T2CON<6>) must be set to enable this mode. In this mode, Timer2 originates clock source ...
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TABLE 10-1: TIMER2/3 REGISTER MAP SFR Name Addr. Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 TMR2 0106 TMR3HLD 0108 TMR3 010A PR2 010C PR3 010E T2CON 0110 TON — TSIDL — T3CON 0112 TON — TSIDL — ...
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... NOTES: DS70116H-page 76 © 2008 Microchip Technology Inc. ...
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... Note: Timer Configuration bit T32 (T4CON<3>) must be set to ‘ bits are respective to the T4CON register. © 2008 Microchip Technology Inc. dsPIC30F5011/5013 • The Timer4/5 module does not support the ADC event trigger feature • Timer4/5 can not be utilized by other peripheral modules, such as input capture and output ...
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... ADC Event Trigger Equal Reset 0 T5IF Event Flag 1 TGATE T5CK Note: In the dsPIC30F5011 device, there is no T5CK pin. Therefore, in this device the following modes should not be used for Timer5: TCS = 1 (16-bit counter) TCS = 0, TGATE = 1 (gated time accumulation) DS70116H-page 78 PR4 Comparator x 16 TMR4 TGATE Q ...
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TABLE 11-1: TIMER4/5 REGISTER MAP SFR Name Addr. Bit 15 Bit 14 Bit 13 Bit 12 TMR4 0114 TMR5HLD 0116 TMR5 0118 PR4 011A PR5 011C T4CON 011E TON — TSIDL — T5CON 0120 TON — TSIDL — Legend: u ...
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... NOTES: DS70116H-page 80 © 2008 Microchip Technology Inc. ...
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... Data Bus Note: Where ‘x’ is shown, reference is made to the registers or bits associated to the respective input capture channels 1 through N. © 2008 Microchip Technology Inc. dsPIC30F5011/5013 12.1 Simple Capture Event Mode The simple capture events in the dsPIC30F product family are: • Capture every falling edge • ...
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... CAPTURE BUFFER OPERATION Each capture channel has an associated FIFO buffer which is four 16-bit words deep. There are two status flags which provide status on the FIFO buffer: • ICBFNE – Input Capture Buffer Not Empty • ICOV – Input Capture Overflow ...
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TABLE 12-1: INPUT CAPTURE REGISTER MAP SFR Name Addr. Bit 15 Bit 14 Bit 13 Bit 12 IC1BUF 0140 IC1CON 0142 — — ICSIDL — IC2BUF 0144 IC2CON 0146 — — ICSIDL — IC3BUF 0148 IC3CON 014A — — ICSIDL ...
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... NOTES: DS70116H-page 84 © 2008 Microchip Technology Inc. ...
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... Note: Where ‘x’ is shown, reference is made to the registers associated with the respective output compare channels 1 through N. © 2008 Microchip Technology Inc. dsPIC30F5011/5013 The key operational features of the output compare module include: • Timer2 and Timer3 Selection mode • Simple Output Compare Match mode • ...
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... Timer2 and Timer3 Selection Mode Each output compare channel can select between one of two 16-bit timers, Timer2 or Timer3. The selection of the timers is controlled by the OCTSEL bit (OCxCON<3>). Timer2 is the default timer resource for the output compare module. 13.2 Simple Output Compare Match Mode When control bits OCM< ...
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... Timer3) is enabled and the TSIDL bit of the selected timer is set to logic ‘0’. © 2008 Microchip Technology Inc. dsPIC30F5011/5013 When the selected TMRx is equal to its respective period register, PRx, the following four events occur on the next increment cycle: • ...
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TABLE 13-1: OUTPUT COMPARE REGISTER MAP SFR Name Addr. Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 OC1RS 0180 OC1R 0182 OC1CON 0184 — — OCSIDL — OC2RS 0186 OC2R 0188 OC2CON 018A — — OCSIDL — OC3RS ...
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... If any transmit data has been written to the buffer register, the contents of the © 2008 Microchip Technology Inc. dsPIC30F5011/5013 transmit buffer are moved to SPIxSR. The received data is thus placed in SPIxBUF and the transmit data in SPIxSR is ready for the next transfer. ...
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... SPI clock cycle. When frame synchronization is enabled, the data transmission starts only on the subsequent transmit edge of the SPI clock. FIGURE 14-1: SPI BLOCK DIAGRAM Read SPIxBUF Receive SDIx bit 0 SDOx SS & FSYNC Control SSx SCKx Note FIGURE 14-2: SPI MASTER/SLAVE CONNECTION ...
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... The transmitter and receiver will stop in Sleep mode. However, register contents are not affected by entering or exiting Sleep mode. © 2008 Microchip Technology Inc. dsPIC30F5011/5013 14.5 SPI Operation During CPU Idle Mode When the device enters Idle mode, all clock sources remain functional. The SPISIDL bit (SPIxSTAT< ...
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TABLE 14-1: SPI1 REGISTER MAP SFR Addr. Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Name SPI1STAT 0220 SPIEN — SPISIDL — SPI1CON 0222 — FRMEN SPIFSD — DISSDO MODE16 SPI1BUF 0224 Legend: — = unimplemented, read ...
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... Thus, the I C module can operate either as a slave master bus. FIGURE 15-1: PROGRAMMER’S MODEL Bit 15 Bit 15 © 2008 Microchip Technology Inc. dsPIC30F5011/5013 15.1.1 VARIOUS I The following types • slave operation with 7-bit address 2 • slave operation with 10-bit address 2 • ...
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... FIGURE 15-2: I C™ BLOCK DIAGRAM Shift SCL Clock SDA Match Detect Stop bit Detect Stop bit Generate Shift Clock DS70116H-page 94 I2CRCV I2CRSR LSB Addr_Match I2CADD Start and Start, Restart, Collision Detect Acknowledge Generation Clock Stretching I2CTRN LSB Reload Control ...
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... ACK received from the master. © 2008 Microchip Technology Inc. dsPIC30F5011/5013 15.3.2 SLAVE RECEPTION If the R_W bit received is a ‘0’ during an address match, then Receive mode is initiated. Incoming bits are sampled on the rising edge of SCL ...
Page 96
... MODE SLAVE TRANSMISSION Once a slave is addressed in this fashion with the full 10-bit address (we will refer to this state as “PRIOR_ADDR_MATCH”), the master can begin sending data bytes for a slave reception operation. 15.4.2 10-BIT MODE SLAVE RECEPTION Once addressed, the master can generate a Repeated ...
Page 97
... Generate a Stop condition on SDA and SCL. 2 • Configure the I C port to receive data. • Generate an ACK condition at the end of a received byte of data. © 2008 Microchip Technology Inc. dsPIC30F5011/5013 2 15. Master Operation The master device generates all of the serial clock 2 C Slave pulses and the Start and Stop conditions ...
Page 98
... BAUD RATE GENERATOR Master mode, the reload value for the BRG is located in the I2CBRG register. When the BRG is loaded with this value, the BRG counts down to ‘0’ and stops until another reload has taken place. If clock arbi- tration is taking place, for instance, the BRG is reloaded when the SCL pin is sampled high ...
Page 99
TABLE 15- REGISTER MAP SFR Name Addr. Bit 15 Bit 14 Bit 13 Bit 12 I2CRCV 0200 — — — — I2CTRN 0202 — — — — I2CBRG 0204 — — — — I2CCON 0206 I2CEN ...
Page 100
... NOTES: DS70116H-page 100 © 2008 Microchip Technology Inc. ...
Page 101
... UTXBRK Data UxTX Parity Note © 2008 Microchip Technology Inc. dsPIC30F5011/5013 16.1 UART Module Overview The key features of the UART module are: • Full-duplex 9-bit data communication • Even, odd or no parity options (for 8-bit data) • One or two Stop bits • ...
Page 102
... FIGURE 16-2: UART RECEIVER BLOCK DIAGRAM LPBACK From UxTX 1 UxRX 0 · Start bit Detect · Parity Check · Stop bit Detect · Shift Clock Generation · Wake Logic DS70116H-page 102 Internal Data Bus 16 Read Write URX8 UxRXREG Low Byte Receive Buffer Control ...
Page 103
... The STSEL bit determines whether one or two Stop bits will be used during data transmission. The default (Power-on) setting of the UART is 8 bits, no parity and 1 Stop bit (typically represented 1). © 2008 Microchip Technology Inc. dsPIC30F5011/5013 16.3 Transmitting Data 16.3.1 TRANSMITTING IN 8-BIT DATA ...
Page 104
... TRANSMIT INTERRUPT The transmit interrupt flag (U1TXIF or U2TXIF) is located in the corresponding interrupt flag register. The transmitter generates an edge to set the UxTXIF bit. The condition for generating the interrupt depends on the UTXISEL control bit UTXISEL = 0, an interrupt is generated when a word is transferred from the transmit buffer to the Transmit Shift register (UxTSR) ...
Page 105
... No further reception can occur until a Stop bit is received. Note that RIDLE goes high when the Stop bit has not yet been received. © 2008 Microchip Technology Inc. dsPIC30F5011/5013 16.6 Address Detect Mode Setting the ADDEN bit (UxSTA<5>) enables this special mode in which a 9th bit (URX8) value of ‘1’ ...
Page 106
... Auto Baud Support To allow the system to determine baud rates of received characters, the input can be optionally linked to a capture input (IC1 for UART1, IC2 for UART2). To enable this mode, the user must program the input capture module to detect the falling and rising edges of the Start bit ...
Page 107
TABLE 16-1: UART1 REGISTER MAP SFR Name Addr. Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 U1MODE 020C UARTEN — USIDL — U1STA 020E UTXISEL — — — UTXBRK UTXEN U1TXREG 0210 — — — — U1RXREG ...
Page 108
... NOTES: DS70116H-page 108 © 2008 Microchip Technology Inc. ...
Page 109
... CAN1 and CAN2) for time-stamping and network synchronization • Low-power Sleep and Idle mode © 2008 Microchip Technology Inc. dsPIC30F5011/5013 The CAN bus module consists of a protocol engine and message buffering/control. The CAN protocol engine handles all functions for receiving and transmitting messages on the CAN bus ...
Page 110
... FIGURE 17-1: CAN BUFFERS AND PROTOCOL ENGINE BLOCK DIAGRAM BUFFERS TXB0 TXB1 Message Queue Control Transmit Byte Sequencer PROTOCOL ENGINE Transmit Logic (1) CiTX Note refers to a particular CAN module (CAN1 or CAN2). DS70116H-page 110 Acceptance Mask TXB2 RXM0 A Acceptance Filter c RXF0 ...
Page 111
... Module Disable mode. The I/O pins will revert to normal I/O function when the module is in the Module Disable mode. © 2008 Microchip Technology Inc. dsPIC30F5011/5013 The module can be programmed to apply a low-pass filter function to the CiRX input line while the module or the CPU is in Sleep mode. The WAKFIL bit (CiCFG2< ...
Page 112
... Message Reception 17.4.1 RECEIVE BUFFERS The CAN bus module has 3 receive buffers. However, one of the receive buffers is always committed to monitoring the bus for incoming messages. This buffer is called the Message Assembly Buffer (MAB). There are 2 receive buffers visible, RXB0 and RXB1, that can ...
Page 113
... SOF occurs. When TXREQ is set, the TXABT (CiTXnCON<6>), TXLARB (CiTXnCON<5>) and TXERR (CiTXnCON<4>) flag bits are automatically cleared. © 2008 Microchip Technology Inc. dsPIC30F5011/5013 Setting TXREQ bit simply flags a message buffer as enqueued for transmission. When the module detects an available bus, it begins transmitting the message which has been determined to have the highest priority ...
Page 114
... TRANSMIT INTERRUPTS Transmit interrupts can be divided into 2 major groups, each including various conditions that generate interrupts: • Transmit Interrupt: At least one of the three transmit buffers is empty (not scheduled) and can be loaded to schedule a message for transmission. Reading the TXnIF flags will indicate which transmit buffer is available and caused the interrupt. • ...
Page 115
... The following requirement must be fulfilled while setting the lengths of the phase segments: Prop Seg + Phase1 Seg > = Phase2 Seg © 2008 Microchip Technology Inc. dsPIC30F5011/5013 17.6.5 SAMPLE POINT The sample point is the point of time at which the bus level is read and interpreted as the value of that ) is a fixed respective bit ...
Page 116
TABLE 17-1: CAN1 REGISTER MAP SFR Name Addr. Bit 15 Bit 14 Bit 13 Bit 12 C1RXF0SID 0300 — — — C1RXF0EIDH 0302 — — — — C1RXF0EIDL 0304 Receive Acceptance Filter 0 Extended Identifier <5:0> C1RXF1SID 0308 — ...
Page 117
TABLE 17-1: CAN1 REGISTER MAP (CONTINUED) SFR Name Addr. Bit 15 Bit 14 Bit 13 Bit 12 C1TX1B2 0358 Transmit Buffer 1 Byte 3 C1TX1B3 035A Transmit Buffer 1 Byte 5 C1TX1B4 035C Transmit Buffer 1 Byte 7 C1TX1CON ...
Page 118
... NOTES: DS70116H-page 118 © 2008 Microchip Technology Inc. ...
Page 119
... CSDOM control bit. This allows other devices to place data on the serial bus during transmission periods not used by the DCI module. © 2008 Microchip Technology Inc. dsPIC30F5011/5013 18.2.3 CSDI PIN The serial data input (CSDI) pin is configured as an input only pin when the module is enabled. ...
Page 120
... FIGURE 18-1: DCI MODULE BLOCK DIAGRAM F OSC Word Size Selection bits Frame Length Selection bits DCI Mode Selection bits Receive Buffer Registers w/Shadow Transmit Buffer Registers w/Shadow DS70116H-page 120 BCG Control bits Sample Rate /4 Generator Frame Synchronization Generator DCI Buffer ...
Page 121
... Note: The COFSG control bits will have no effect in AC-Link mode since the frame length is set to 256 CSCK periods by the protocol. © 2008 Microchip Technology Inc. dsPIC30F5011/5013 18.3.4 FRAME SYNC MODE CONTROL BITS The type of frame sync signal is selected using the by ...
Page 122
... SLAVE FRAME SYNC OPERATION When the DCI module is operating as a frame sync slave (COFSD = 1), data transfers are controlled by the codec device attached to the DCI module. The COFSM control bits control how the DCI module responds to incoming COFS signals. In the Multi-Channel mode, a new data frame transfer will begin one CSCK cycle after the COFS pin is sampled high (see Figure 18-2) ...
Page 123
... When the CSCK signal is applied externally (CSCKD = 1), the BCG<11:0> bits have no effect on the operation of the DCI module. © 2008 Microchip Technology Inc. dsPIC30F5011/5013 EQUATION 18-2: The required bit clock frequency will be determined by the system sampling rate and frame size. Typical bit ...
Page 124
... SAMPLE CLOCK EDGE CONTROL BIT The sample clock edge (CSCKE) control bit determines the sampling edge for the CSCK signal. If the CSCK bit is cleared (default), data will be sampled on the falling edge of the CSCK signal. The AC-Link protocols and most Multi-Channel formats require that data be sampled on the falling edge of the CSCK signal ...
Page 125
... DCI module. © 2008 Microchip Technology Inc. dsPIC30F5011/5013 18.3.16 TRANSMIT STATUS BITS There are two transmit status bits in the DCISTAT SFR. The TMPTY bit is set when the contents of the transmit buffer registers are transferred to the transmit shadow registers ...
Page 126
... SLOT STATUS BITS The SLOT<3:0> status bits in the DCISTAT SFR indicate the current active time slot. These bits will correspond to the value of the frame sync generator counter. The user may poll these status bits in software when a DCI interrupt occurs to determine what time slot data was last received and which time slot data should be loaded into the TXBUF registers ...
Page 127
... TSCON and RSCON SFRs. Since the total available buffer length is 64 bits, it would take 4 consecutive interrupts to transfer the AC-Link frame. The application software must keep track of the current AC-Link frame segment. © 2008 Microchip Technology Inc. dsPIC30F5011/5013 2 18 Mode Operation 2 ...
Page 128
TABLE 18-2: DCI REGISTER MAP SFR Name Addr. Bit 15 Bit 14 Bit 13 Bit 12 DCICON1 0240 DCIEN — DCISIDL — DCICON2 0242 — — — — DCICON3 0244 — — — — DCISTAT 0246 — — — ...
Page 129
... AN14 1111 AN15 V AN1 © 2008 Microchip Technology Inc. dsPIC30F5011/5013 The ADC module has six 16-bit registers: • ADC Control Register 1 (ADCON1) • ADC Control Register 2 (ADCON2) • ADC Control Register 3 (ADCON3) • ADC Input Select Register (ADCHS) • ADC Port Configuration Register (ADPCFG) • ...
Page 130
... ADC Result Buffer The ADC module contains a 16-word, dual port, read-only buffer called ADCBUF0...ADCBUFF, to buffer the ADC results. The RAM is 12 bits wide, but the data obtained is represented in one of four different 16-bit data formats. The contents of the sixteen ADC Result Buffer registers, ADCBUF0 through ADCBUFF, cannot be written by user software ...
Page 131
... ADC CONVERSION CLOCK (0.5*(ADCS<5:0> © 2008 Microchip Technology Inc. dsPIC30F5011/5013 The internal RC oscillator is selected by setting the ADRC bit. For correct ADC conversions, the ADC conversion clock (T ) must be selected to ensure a minimum T AD time of 334 nsec (for V “Electrical Characteristics” for minimum T other operating conditions ...
Page 132
... ADC Speeds The dsPIC30F 12-bit ADC specifications permit a max- imum of 200 ksps sampling rate. The table below sum- marizes the conversion speeds for the dsPIC30F 12-bit ADC and the required operating conditions. TABLE 19-1: 12-BIT ADC EXTENDED CONVERSION RATES ...
Page 133
... Set SSRC<2.0> = 111 in the ADCON1 register to enable the auto convert option. • Enable automatic sampling by setting the ASAM control bit in the ADCON1 register. • Write the SMPI<3.0> control bits in the ADCON2 register for the desired number of conversions between interrupts. © 2008 Microchip Technology Inc. dsPIC30F5011/5013 ...
Page 134
... FIGURE 19-3: CONVERTING 1 CHANNEL AT 200 KSPS, AUTO-SAMPLE START SAMPLING TIME T SAMP = ADCLK SAMP DONE ADCBUF0 ADCBUF1 Instruction Execution BSET ADCON1, ASAM 19.8 ADC Acquisition Requirements The analog input model of the 12-bit ADC is shown in Figure 19-4. The total sampling time for the ADC is a function of the internal amplifier settling time and the holding capacitor charge time ...
Page 135
... If the ADC interrupt is enabled, the device wakes up from Sleep. If the ADC interrupt is not enabled, the ADC module is turned off, although the ADON bit remains set. © 2008 Microchip Technology Inc. dsPIC30F5011/5013 19.10.2 A/D OPERATION DURING CPU IDLE MODE The ADSIDL bit selects if the module stops on Idle or continues on Idle ...
Page 136
... FIGURE 19-5: ADC OUTPUT DATA FORMATS RAM Contents: Read to Bus: Signed Fractional d11 d10 d09 d08 d07 d06 d05 d04 d03 d02 d01 d00 Fractional d11 d10 d09 d08 d07 d06 d05 d04 d03 d02 d01 d00 Signed Integer d11 d11 d11 d11 d11 d10 d09 d08 d07 d06 d05 d04 d03 d02 d01 d00 ...
Page 137
TABLE 19-2: A/D CONVERTER REGISTER MAP SFR Addr. Bit 15 Bit 14 Bit 13 Bit 12 Name ADCBUF0 0280 — — — — ADCBUF1 0282 — — — — ADCBUF2 0284 — — — — ADCBUF3 0286 — — — ...
Page 138
... NOTES: DS70116H-page 138 © 2008 Microchip Technology Inc. ...
Page 139
... In Idle mode, the clock sources are still active but the CPU is shut-off. The RC oscillator option saves system cost while the LP crystal option saves power. © 2008 Microchip Technology Inc. dsPIC30F5011/5013 20.1 Oscillator System Overview The dsPIC30F oscillator system has the following features: • ...
Page 140
... TABLE 20-1: OSCILLATOR OPERATING MODES Oscillator Mode XTL 200 kHz-4 MHz crystal on OSC1:OSC2 MHz-10 MHz crystal on OSC1:OSC2 PLL 4x 4 MHz-10 MHz crystal on OSC1:OSC2, 4x PLL enabled PLL 8x 4 MHz-10 MHz crystal on OSC1:OSC2, 8x PLL enabled PLL 16x 4 MHz-10 MHz crystal on OSC1:OSC2, 16x PLL enabled ...
Page 141
... OSCILLATOR SYSTEM BLOCK DIAGRAM OSC1 Primary Oscillator OSC2 TUN<3:0> 4 Internal Fast RC Oscillator (FRC) POR Done SOSCO 32 kHz LP Oscillator SOSCI © 2008 Microchip Technology Inc. dsPIC30F5011/5013 F PLL PLL x4, x8, x16 PLL Lock Primary Osc Primary Oscillator Stability Detector Oscillator Start-up Clock Timer ...
Page 142
... Oscillator Configurations 20.2.1 INITIAL CLOCK SOURCE SELECTION While coming out of Power-on Reset or Brown-out Reset, the device selects its clock source based on: a) FOS<1:0> Configuration bits, which select one of four oscillator groups, and b) FPR<3:0> Configuration bits, which select one of 13 oscillator choices within the primary group. ...
Page 143
... PLL multiplier (respectively) is applied. Note: When a 16x PLL is used, the FRC frequency must not be tuned to a frequency greater than 7.5 MHz. © 2008 Microchip Technology Inc. dsPIC30F5011/5013 TABLE 20-4: TUN<3:0> Bits 0111 0110 0101 ...
Page 144
... FAIL-SAFE CLOCK MONITOR The Fail-Safe Clock Monitor (FSCM) allows the device to continue to operate even in the event of an oscillator failure. The FSCM function is enabled by appropriately programming the FCKSM Configuration bits (clock switch and monitor selection bits) in the FOSC Device Configuration register. If the FSCM function is enabled, ...
Page 145
... POR also selects the device clock source identified by the oscillator configuration fuses. © 2008 Microchip Technology Inc. dsPIC30F5011/5013 Different registers are affected in different ways by var- ious Reset conditions. Most registers are not affected by a WDT wake-up since this is viewed as the resump- tion of normal operation ...
Page 146
... FIGURE 20-3: TIME-OUT SEQUENCE ON POWER-UP (MCLR TIED MCLR INTERNAL POR OST TIME-OUT PWRT TIME-OUT INTERNAL Reset FIGURE 20-4: TIME-OUT SEQUENCE ON POWER-UP (MCLR NOT TIED MCLR INTERNAL POR OST TIME-OUT PWRT TIME-OUT INTERNAL Reset FIGURE 20-5: TIME-OUT SEQUENCE ON POWER-UP (MCLR NOT TIED TO V ...
Page 147
... The BOR will select the clock source based on the device Configuration bit values (FOS<1:0> and © 2008 Microchip Technology Inc. dsPIC30F5011/5013 FPR<3:0>). Furthermore Oscillator mode is selected, the BOR will activate the Oscillator Start-up Timer (OST). The system clock is held until OST expires ...
Page 148
... Table 20-5 shows the Reset conditions for the RCON register. Since the control bits within the RCON register are R/W, the information in the table implies that all the bits are negated prior to the action specified in the condition column. TABLE 20-5: ...
Page 149
... Illegal Operation Reset 0x000000 Legend unchanged unknown unimplemented bit, read as ‘0’ Note 1: When the wake-up is due to an enabled interrupt, the PC is loaded with the corresponding interrupt vector. © 2008 Microchip Technology Inc. dsPIC30F5011/5013 TRAPR IOPUWR EXTR SWR WDTO IDLE SLEEP POR BOR ...
Page 150
... Watchdog Timer (WDT) 20.4.1 WATCHDOG TIMER OPERATION The primary function of the Watchdog Timer (WDT reset the processor in the event of a software malfunction. The WDT is a free-running timer which runs off an on-chip RC oscillator, requiring no external component. Therefore, the WDT timer will continue to operate even if the main processor clock (e ...
Page 151
... Any Reset other than POR will set the Idle Status bit POR, the Idle bit is cleared. © 2008 Microchip Technology Inc. dsPIC30F5011/5013 If Watchdog Timer is enabled, then the processor will wake-up from Idle mode upon WDT time-out. The Idle and WDTO status bits are both set. ...
Page 152
... Peripheral Module Disable (PMD) Registers The Peripheral Module Disable (PMD) registers pro- vide a method to disable a peripheral module by stop- ping all clock sources supplied to that module. When a peripheral is disabled via the appropriate PMD control bit, the peripheral minimum power consumption state ...
Page 153
TABLE 20-7: SYSTEM INTEGRATION REGISTER MAP SFR Addr. Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Name RCON 0740 TRAPR IOPUWR BGST LVDEN OSCCON 0742 TUN3 TUN2 COSC<1:0> TUN1 PMD1 0770 T5MD T4MD T3MD T2MD T1MD PMD2 0772 ...
Page 154
... NOTES: DS70116H-page 154 © 2008 Microchip Technology Inc. ...
Page 155
... The file register specified by the value ‘f’ • The destination, which could either be the file register ‘f’ or the W0 register, which is denoted as ‘WREG’ © 2008 Microchip Technology Inc. dsPIC30F5011/5013 Most bit-oriented rotate/shift instructions) have two operands: • The W register (with or without an address modifier) or file register (specified by the value of ‘ ...
Page 156
... All instructions are a single word, except for certain double word instructions, which were made double word instructions so that all the required information is available in these 48 bits. In the second word, the 8 Most Significant bits are ‘0’s. If this second word is executed as an instruction (by itself), it will execute as a NOP ...
Page 157
... Y data space prefetch address register for DSP instructions ∈ {[W10]+=6, [W10]+=4, [W10]+=2, [W10], [W10]-=6, [W10]-=4, [W10]-=2, [W11]+=6, [W11]+=4, [W11]+=2, [W11], [W11]-=6, [W11]-=4, [W11]-=2, [W11+W12], none} Y data space prefetch destination register for DSP instructions ∈ {W4..W7} Wyd © 2008 Microchip Technology Inc. dsPIC30F5011/5013 Description DS70116H-page 157 ...
Page 158
... TABLE 21-2: INSTRUCTION SET OVERVIEW Base Assembly Instr Assembly Syntax Mnemonic # 1 ADD ADD Acc ADD f ADD f,WREG ADD #lit10,Wn ADD Wb,Ws,Wd ADD Wb,#lit5,Wd ADD Wso,#Slit4,Acc 2 ADDC ADDC f ADDC f,WREG ADDC #lit10,Wn ADDC Wb,Ws,Wd ADDC Wb,#lit5,Wd 3 AND AND f AND f,WREG ...
Page 159
... DEC2 DEC2 f DEC2 f,WREG DEC2 Ws,Wd 28 DISI DISI #lit14 © 2008 Microchip Technology Inc. dsPIC30F5011/5013 # of Description Words Bit Toggle f Bit Toggle Ws Bit Test f, Skip if Clear Bit Test Ws, Skip if Clear Bit Test f, Skip if Set Bit Test Ws, Skip if Set Bit Test f Bit Test Bit Test Bit Test Ws< ...
Page 160
... TABLE 21-2: INSTRUCTION SET OVERVIEW (CONTINUED) Base Assembly Instr Assembly Syntax Mnemonic # 29 DIV DIV.S Wm,Wn DIV.SD Wm,Wn DIV.U Wm,Wn DIV.UD Wm,Wn 30 DIVF DIVF Wm, #lit14,Expr DO Wn,Expr Wm*Wm,Acc,Wx,Wy,Wxd 33 EDAC EDAC Wm*Wm,Acc,Wx,Wy,Wxd 34 EXCH EXCH Wns,Wnd 35 FBCL FBCL Ws,Wnd 36 FF1L FF1L Ws,Wnd 37 FF1R FF1R ...
Page 161
... Ws,Wd 66 RRNC RRNC f RRNC f,WREG RRNC Ws,Wd © 2008 Microchip Technology Inc. dsPIC30F5011/5013 # of Description Words Multiply Accumulator Square Wm to Accumulator -(Multiply Wm by Wn) to Accumulator Multiply and Subtract from Accumulator {Wnd+1, Wnd} = signed(Wb) * signed(Ws) {Wnd+1, Wnd} = signed(Wb) * unsigned(Ws) {Wnd+1, Wnd} = unsigned(Wb) * signed(Ws) ...
Page 162
... TABLE 21-2: INSTRUCTION SET OVERVIEW (CONTINUED) Base Assembly Instr Assembly Syntax Mnemonic # 67 SAC SAC Acc,#Slit4,Wdo SAC.R Acc,#Slit4,Wdo Ws,Wnd 69 SETM SETM f SETM WREG SETM Ws 70 SFTAC SFTAC Acc,Wn SFTAC Acc,#Slit6 f,WREG SL Ws,Wd SL Wb,Wns,Wnd SL Wb,#lit5,Wnd 72 SUB SUB Acc ...
Page 163
... MPLAB PM3 Device Programmer - PICkit™ 2 Development Programmer • Low-Cost Demonstration and Development Boards and Evaluation Kits © 2008 Microchip Technology Inc. dsPIC30F5011/5013 22.1 MPLAB Integrated Development Environment Software The MPLAB IDE software brings an ease of software development previously unseen in the 8/16-bit microcontroller market ...
Page 164
... MPASM Assembler The MPASM Assembler is a full-featured, universal macro assembler for all PIC MCUs. The MPASM Assembler generates relocatable object files for the MPLINK Object Linker, Intel files, MAP files to detail memory usage and symbol reference, absolute LST files that contain source lines and generated machine code and COFF files for debugging ...
Page 165
... Microchip Technology Inc. dsPIC30F5011/5013 22.9 MPLAB ICD 2 In-Circuit Debugger Microchip’s In-Circuit Debugger, MPLAB ICD powerful, ...
Page 166
... PICSTART Plus Development Programmer The PICSTART Plus Development Programmer is an easy-to-use, low-cost, prototype programmer. It connects to the PC via a COM (RS-232) port. MPLAB Integrated Development Environment software makes using the programmer simple and efficient. The PICSTART Plus Development Programmer supports most PIC devices in DIP packages pins. ...
Page 167
... V Range Temp Range DD 4.75-5.5V -40°C to 85°C 4.75-5.5V -40°C to 125°C 3.0-3.6V -40°C to 85°C 3.0-3.6V -40°C to 125°C 2.5-3.0V -40°C to 85°C © 2008 Microchip Technology Inc. dsPIC30F5011/5013 (1) (except V and MCLR) ............................................... -0. ....................................................................................................... 0V to +13.25V ) .......................................................................................................... ± > ................................................................................................... ± (2) ..............................................................................................................200 mA pin, inducing currents greater than 80 mA, may cause latchup. ...
Page 168
... TABLE 23-2: THERMAL OPERATING CONDITIONS Rating dsPIC30F501x-30I Operating Junction Temperature Range Operating Ambient Temperature Range dsPIC30F501x-20I Operating Junction Temperature Range Operating Ambient Temperature Range dsPIC30F501x-20E Operating Junction Temperature Range Operating Ambient Temperature Range Power Dissipation: Internal chip power dissipation: ∑ ...
Page 169
... All I/O pins are configured as Inputs and pulled to V MCLR = V , WDT, FSCM, LVD and BOR are disabled. CPU, SRAM, Program Memory and Data Memory DD are operational. No peripheral modules are operating. © 2008 Microchip Technology Inc. dsPIC30F5011/5013 ) DD Standard Operating Conditions: 2.5V to 5.5V (unless otherwise stated) -40°C ≤ T ≤ ...
Page 170
... TABLE 23-6: DC CHARACTERISTICS: IDLE CURRENT (I DC CHARACTERISTICS Parameter (1,2) Typical Max No. Idle Current (I ): Core OFF Clock ON Base Current IDLE DC50a 4.8 7.2 DC50b 4.9 7.3 DC50c 5.0 7.5 DC50e 8.9 13.3 DC50f 8.8 13.2 DC50g 8.8 13.2 DC51a 1.6 2.4 DC51b 1 ...
Page 171
... The Δ current is the additional current consumed when the module is enabled. This current should be 3: added to the base I current. PD © 2008 Microchip Technology Inc. dsPIC30F5011/5013 Standard Operating Conditions: 2.5V to 5.5V (unless otherwise stated) -40°C ≤ T ≤ +85°C for Industrial Operating temperature A -40° ...
Page 172
... TABLE 23-8: DC CHARACTERISTICS: I/O PIN INPUT SPECIFICATIONS DC CHARACTERISTICS Param Symbol Characteristic No. V Input Low Voltage IL DI10 I/O pins: with Schmitt Trigger buffer DI15 MCLR DI16 OSC1 (in XT, HS and LP modes) DI17 OSC1 (in RC mode) DI18 SDA, SCL DI19 SDA, SCL V Input High Voltage ...
Page 173
... These parameters are characterized but not tested in manufacturing. FIGURE 23-1: LOW-VOLTAGE DETECT CHARACTERISTICS V DD LV10 LVDIF (LVDIF set by hardware) © 2008 Microchip Technology Inc. dsPIC30F5011/5013 Standard Operating Conditions: 2.5V to 5.5V (unless otherwise stated) -40°C ≤ T Operating temperature -40°C ≤ T (1) Min Typ ...
Page 174
... TABLE 23-10: ELECTRICAL CHARACTERISTICS: LVDL DC CHARACTERISTICS Param Symbol Characteristic No. LV10 V LVDL Voltage on V PLVD high to low LV15 V External LVD input pin LVDIN threshold voltage Note 1: These parameters are characterized but not tested in manufacturing. 2: These values not in usable operating range. FIGURE 23-2: ...
Page 175
... EB DD Note 1: Data in “Typ” column is at 5V, 25°C unless otherwise stated. 2: These parameters are characterized but not tested in manufacturing. © 2008 Microchip Technology Inc. dsPIC30F5011/5013 Standard Operating Conditions: 2.5V to 5.5V (unless otherwise stated) -40°C ≤ T Operating temperature -40°C ≤ T (1) ...
Page 176
... AC Characteristics and Timing Parameters The information contained in this section defines dsPIC30F AC characteristics and timing parameters. TABLE 23-13: TEMPERATURE AND VOLTAGE SPECIFICATIONS – CHARACTERISTICS FIGURE 23-3: LOAD CONDITIONS FOR DEVICE TIMING SPECIFICATIONS Load Condition 1 – for all pins except OSC2 ...
Page 177
... Measurements are taken ERC modes. The CLKOUT signal is measured on the OSC2 pin. CLKOUT is low for the Q1-Q2 period (1/2 T © 2008 Microchip Technology Inc. dsPIC30F5011/5013 Standard Operating Conditions: 2.5V to 5.5V (unless otherwise stated) -40°C ≤ T Operating temperature -40° ...
Page 178
... TABLE 23-15: PLL CLOCK TIMING SPECIFICATIONS (V AC CHARACTERISTICS Param Symbol Characteristic No. OS50 F PLL Input Frequency Range PLLI OS51 F On-Chip PLL Output SYS OS52 T PLL Start-up Time (Lock Time) LOC Note 1: These parameters are characterized but not tested in manufacturing. 2: Data in “Typ” column is at 5V, 25°C unless otherwise stated. Parameters are for design guidance only and are not tested ...
Page 179
... TABLE 23-19: AC CHARACTERISTICS: INTERNAL LPRC ACCURACY AC CHARACTERISTICS Param Characteristic No. (1) LPRC @ Freq. = 512 kHz OS65A OS65B OS65C Note 1: Change of LPRC frequency as V © 2008 Microchip Technology Inc. dsPIC30F5011/5013 (3) T MIPS MIPS CY (1) (2) (μsec) w/o PLL w PLL x4 20.0 0.05 1.0 1.0 ...
Page 180
... FIGURE 23-5: CLKOUT AND I/O TIMING CHARACTERISTICS I/O Pin (Input) I/O Pin Old Value (Output) Note: Refer to Figure 23-3 for load conditions. TABLE 23-20: CLKOUT AND I/O TIMING REQUIREMENTS AC CHARACTERISTICS Param Symbol Characteristic No. DO31 T R Port output rise time IO DO32 ...
Page 181
... TIMER TIMING CHARACTERISTICS V DD SY12 MCLR Internal POR SY11 PWRT Time-out SY30 OSC Time-out Internal RESET Watchdog Timer RESET I/O Pins SY35 FSCM Delay Note: Refer to Figure 23-3 for load conditions. © 2008 Microchip Technology Inc. dsPIC30F5011/5013 SY10 SY20 SY13 SY13 DS70116H-page 181 ...
Page 182
... TABLE 23-21: RESET, WATCHDOG TIMER, OSCILLATOR START-UP TIMER, POWER-UP TIMER AND BROWN-OUT RESET TIMING REQUIREMENTS AC CHARACTERISTICS Param Symbol Characteristic No. SY10 TmcL MCLR Pulse Width (low) SY11 T Power-up Timer Period PWRT SY12 T Power-on Reset Delay POR SY13 T I/O High-impedance from MCLR ...
Page 183
... BGAP Note 1: These parameters are characterized but not tested in manufacturing. 2: Data in “Typ” column is at 5V, 25°C unless otherwise stated. © 2008 Microchip Technology Inc. dsPIC30F5011/5013 SY40 Standard Operating Conditions: 2.5V to 5.5V (unless otherwise stated) -40°C ≤ T Operating temperature -40°C ≤ T ...
Page 184
... FIGURE 23-8: TYPE A, B AND C TIMER EXTERNAL CLOCK TIMING CHARACTERISTICS TxCK TMRX Note: Refer to Figure 23-3 for load conditions. TABLE 23-23: TYPE A TIMER (TIMER1) EXTERNAL CLOCK TIMING REQUIREMENTS AC CHARACTERISTICS Param Symbol Characteristic No. TA10 T H TxCK High Time TX TA11 T L TxCK Low Time ...
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... TxCK Input Period Synchronous, TC20 T Delay from External TxCK Clock CKEXTMRL Edge to Timer Increment Note: Timer3 and Timer5 are Type C. © 2008 Microchip Technology Inc. dsPIC30F5011/5013 Standard Operating Conditions: 2.5V to 5.5V (unless otherwise stated) -40°C ≤ T Operating temperature -40°C ≤ T Min Typ Synchronous, ...
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... FIGURE 23-9: INPUT CAPTURE (CAPx) TIMING CHARACTERISTICS IC X Note: Refer to Figure 23-3 for load conditions. TABLE 23-26: INPUT CAPTURE TIMING REQUIREMENTS AC CHARACTERISTICS Param Symbol Characteristic No. IC10 TccL ICx Input Low Time IC11 TccH ICx Input High Time IC15 TccP ICx Input Period Note 1: These parameters are characterized but not tested in manufacturing ...
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... These parameters are characterized but not tested in manufacturing. 2: Data in “Typ” column is at 5V, 25°C unless otherwise stated. Parameters are for design guidance only and are not tested. © 2008 Microchip Technology Inc. dsPIC30F5011/5013 OC10 OC11 Standard Operating Conditions: 2.5V to 5.5V (unless otherwise stated) -40° ...
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... FIGURE 23-11: OC/PWM MODULE TIMING CHARACTERISTICS OCFA/OCFB OC15 OCx TABLE 23-28: SIMPLE OC/PWM MODE TIMING REQUIREMENTS AC CHARACTERISTICS Param Symbol Characteristic No. OC15 T Fault Input to PWM I/O FD Change OC20 T Fault Input Pulse Width FLT Note 1: These parameters are characterized but not tested in manufacturing. ...
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... CSCK (SCKE = 1) COFS CS55 CS56 CS35 CS51 CS50 HIGH-Z CSDO CSDI Note: Refer to Figure 23-3 for load conditions. © 2008 Microchip Technology Inc. dsPIC30F5011/5013 2 S MODES) TIMING CHARACTERISTICS CS11 CS10 CS21 CS20 MSb CS30 MSb IN CS40 CS41 CS20 CS21 70 LSb ...
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... TABLE 23-29: DCI MODULE (MULTICHANNEL CHARACTERISTICS Param Symbol Characteristic No. CS10 Tc CSCK Input Low Time SCKL (CSCK pin is an input) CSCK Output Low Time (CSCK pin is an output) CS11 Tc CSCK Input High Time SCKH (CSCK pin is an input) CSCK Output High Time ...
Page 191
... These parameters are characterized but not tested in manufacturing. 2: These values assume BIT_CLK frequency is 12.288 MHz. 3: Data in “Typ” column is at 5V, 25°C unless otherwise stated. Parameters are for design guidance only and are not tested. © 2008 Microchip Technology Inc. dsPIC30F5011/5013 CS62 CS21 CS71 CS72 CS76 CS76 Standard Operating Conditions: 2 ...
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... FIGURE 23-14: SPI MODULE MASTER MODE (CKE = 0) TIMING CHARACTERISTICS SCKx (CKP = 0) SP11 SCKx (CKP = 1) SP35 SDOx SP31 SDIx MSb IN SP40 SP41 Note: Refer to Figure 23-3 for load conditions. TABLE 23-31: SPI MASTER MODE (CKE = 0) TIMING REQUIREMENTS AC CHARACTERISTICS Param Symbol Characteristic No ...
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... Data in “Typ” column is at 5V, 25°C unless otherwise stated. Parameters are for design guidance only and are not tested. 3: The minimum clock period for SCK is 100 ns. Therefore, the clock generated in Master mode must not violate this specification. 4: Assumes 50 pF load on all SPI pins. © 2008 Microchip Technology Inc. dsPIC30F5011/5013 SP10 SP21 SP35 SP20 LSb BIT14 - - - - - -1 BIT14 - - - -1 LSb IN Standard Operating Conditions: 2 ...
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... FIGURE 23-16: SPI MODULE SLAVE MODE (CKE = 0) TIMING CHARACTERISTICS SS X SP50 SCK X (CKP = 0) SP71 SCK X (CKP = 1) SP35 SDO X SDI SDI X SP40 Note: Refer to Figure 23-3 for load conditions. TABLE 23-33: SPI MODULE SLAVE MODE (CKE = 0) TIMING REQUIREMENTS AC CHARACTERISTICS Param Symbol Characteristic No ...
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... SCK X (CKP = 0) SP71 SCK X (CKP = 1) MSb SDO X SDI SDI X MSb IN SP41 SP40 Note: Refer to Figure 23-3 for load conditions. © 2008 Microchip Technology Inc. dsPIC30F5011/5013 SP70 SP73 SP35 SP72 SP52 BIT14 - - - - - -1 LSb SP30,SP31 BIT14 - - - -1 LSb IN SP52 SP72 SP73 SP51 DS70116H-page 195 ...
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... TABLE 23-34: SPI MODULE SLAVE MODE (CKE = 1) TIMING REQUIREMENTS AC CHARACTERISTICS Param Symbol Characteristic No. TscL SP70 SCK Input Low Time X SP71 TscH SCK Input High Time X SP72 TscF SCK Input Fall Time X SP73 TscR SCK Input Rise Time X SP30 TdoF SDO ...
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... I C™ BUS DATA TIMING CHARACTERISTICS (MASTER MODE) IM20 SCL IM11 IM10 SDA In IM40 SDA Out Note: Refer to Figure 23-3 for load conditions. © 2008 Microchip Technology Inc. dsPIC30F5011/5013 IM11 IM10 IM26 IM25 IM40 IM34 IM33 Stop Condition IM21 IM33 IM45 ...
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... TABLE 23-35: I C™ BUS DATA TIMING REQUIREMENTS (MASTER MODE) AC CHARACTERISTICS Param Symbol Characteristic No. IM10 T : Clock Low Time 100 kHz mode LO SCL 400 kHz mode 1 MHz mode IM11 T : Clock High Time 100 kHz mode HI SCL 400 kHz mode 1 MHz mode ...
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... SDA Start Condition 2 FIGURE 23-21: I C™ BUS DATA TIMING CHARACTERISTICS (SLAVE MODE) IS20 SCL IS30 IS31 SDA In IS40 SDA Out © 2008 Microchip Technology Inc. dsPIC30F5011/5013 IS33 IS11 IS10 IS26 IS25 IS40 IS34 Stop Condition IS21 IS33 IS45 DS70116H-page 199 ...
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... TABLE 23-36: I C™ BUS DATA TIMING REQUIREMENTS (SLAVE MODE) AC CHARACTERISTICS Param Symbol Characteristic No. IS10 T : Clock Low Time LO SCL IS11 T : Clock High Time HI SCL IS20 T : SDA and SCL F SCL Fall Time IS21 T : SDA and SCL R SCL Rise Time IS25 T : Data Input ...