DSPIC30F5011-20I/PTG Microchip Technology, DSPIC30F5011-20I/PTG Datasheet - Page 215

• Manufacturer Part Number: DSPIC30F5011-20I/PTG
• Description: IC, DSC, 16BIT, 66KB, 40MHZ 5.5V TQFP-64
• Manufacturer: Microchip Technology
• Series: DsPIC30Fr

Specifications of DSPIC30F5011-20I/PTG

• Core Frequency: 40MHz
• Core Supply Voltage: 5.5V
• Embedded Interface Type: CAN, I2C, SPI, UART
• No. Of I/o's: 52
• Flash Memory Size: 66KB
• Supply Voltage Range: 2.5V To 5.5V
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

I
I
I
I
I
I
Idle Current (I
In-Circuit Serial Programming (ICSP) ......................... 49, 139
Input Capture (CAPX) Timing Characteristics .................. 186
Input Capture Module ......................................................... 81
Input Capture Operation During Sleep and Idle Modes ...... 82
Input Capture Timing Requirements ................................. 186
Input Change Notification Module ....................................... 66
Instruction Addressing Modes............................................. 43
Instruction Set
© 2008 Microchip Technology Inc.
2
2
2
2
2
2
C 10-bit Slave Mode Operation ........................................ 95
C 7-bit Slave Mode Operation .......................................... 95
C Master Mode Operation ................................................ 97
C Master Mode Support ................................................... 97
C Module .......................................................................... 93
S Mode Operation .......................................................... 127
Parallel (PIO) .............................................................. 61
Reception.................................................................... 96
Transmission............................................................... 96
Reception.................................................................... 95
Transmission............................................................... 95
Baud Rate Generator.................................................. 98
Clock Arbitration.......................................................... 98
Multi-Master Communication, Bus Collision
and Bus Arbitration ..................................................... 98
Reception.................................................................... 97
Transmission............................................................... 97
Addresses ................................................................... 95
Bus Data Timing Characteristics
Bus Data Timing Requirements
Bus Start/Stop Bits Timing Characteristics
General Call Address Support .................................... 97
Interrupts..................................................................... 97
IPMI Support ............................................................... 97
Operating Function Description .................................. 93
Operation During CPU Sleep and Idle Modes ............ 98
Pin Configuration ........................................................ 93
Programmer’s Model................................................... 93
Register Map............................................................... 99
Registers..................................................................... 93
Slope Control .............................................................. 97
Software Controlled Clock Stretching
(STREN = 1) ............................................................... 96
Various Modes ............................................................ 93
Data Justification....................................................... 127
Frame and Data Word Length Selection................... 127
Interrupts..................................................................... 82
Register Map............................................................... 83
CPU Idle Mode............................................................ 82
CPU Sleep Mode ........................................................ 82
dsPIC30F5011 Register Map (Bits 15-8) .................... 66
dsPIC30F5011 Register Map (Bits 7-0) ...................... 66
dsPIC30F5013 Register Map (Bits 15-8) .................... 66
dsPIC30F5013 Register Map (Bits 7-0) ...................... 66
File Register Instructions ............................................ 43
Fundamental Modes Supported.................................. 43
MAC Instructions......................................................... 44
MCU Instructions ........................................................ 43
Move and Accumulator Instructions............................ 44
Other Instructions........................................................ 44
Master Mode ..................................................... 197
Slave Mode ....................................................... 199
Master Mode ..................................................... 198
Slave Mode ....................................................... 200
Master Mode ..................................................... 197
Slave Mode ....................................................... 199
IDLE
) ............................................................ 170
Internal Clock Timing Examples ....................................... 178
Internet Address ............................................................... 219
Interrupt Controller
Interrupt Priority .................................................................. 38
Interrupt Sequence ............................................................. 41
Interrupts ............................................................................ 37
L
Load Conditions................................................................ 176
Low Voltage Detect (LVD) ................................................ 150
Low-Voltage Detect Characteristics.................................. 173
LVDL Characteristics ........................................................ 174
M
Memory Organization ......................................................... 25
Microchip Internet Web Site.............................................. 219
Modes of Operation
Modulo Addressing ............................................................. 44
MPLAB ASM30 Assembler, Linker, Librarian ................... 164
MPLAB ICD 2 In-Circuit Debugger ................................... 165
MPLAB ICE 2000 High-Performance Universal
MPLAB Integrated Development Environment
Software ........................................................................... 163
MPLAB PM3 Device Programmer .................................... 165
MPLAB REAL ICE In-Circuit Emulator System ................ 165
MPLINK Object Linker/MPLIB Object Librarian ................ 164
N
NVM
O
OC/PWM Module Timing Characteristics ......................... 188
Operating Current (I
Oscillator
Oscillator Selection ........................................................... 139
Oscillator Start-up Timer
dsPIC30F5011/5013
Overview................................................................... 158
Summary .................................................................. 155
Register Map .............................................................. 42
Traps .......................................................................... 39
Interrupt Stack Frame................................................. 41
Core Register Map ..................................................... 34
Disable...................................................................... 111
Initialization............................................................... 111
Listen All Messages.................................................. 111
Listen Only................................................................ 111
Loopback .................................................................. 111
Normal Operation ..................................................... 111
Applicability................................................................. 46
Incrementing Buffer Operation Example .................... 45
Start and End Address ............................................... 45
W Address Register Selection.................................... 45
In-Circuit Emulator.................................................... 165
Register Map .............................................................. 53
Configurations .......................................................... 142
Operating Modes (Table).......................................... 140
System Overview...................................................... 139
Timing Characteristics .............................................. 181
Timing Requirements ............................................... 182
Fail-Safe Clock Monitor .................................... 144
Fast RC (FRC).................................................. 143
Initial Clock Source Selection ........................... 142
Low Power RC (LPRC)..................................... 143
LP Oscillator Control......................................... 142
Phase Locked Loop (PLL) ................................ 143
Start-up Timer (OST)........................................ 142
DD
) .................................................... 169
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