IC PIC MCU FLASH 32KX16 100TQFP

PIC24HJ64GP510-E/PT

Manufacturer Part NumberPIC24HJ64GP510-E/PT
DescriptionIC PIC MCU FLASH 32KX16 100TQFP
ManufacturerMicrochip Technology
SeriesPIC® 24H
PIC24HJ64GP510-E/PT datasheets
 


Specifications of PIC24HJ64GP510-E/PT

Core ProcessorPICCore Size16-Bit
Speed40 MIPsConnectivityCAN, I²C, IrDA, LIN, SPI, UART/USART
PeripheralsBrown-out Detect/Reset, DMA, POR, PWM, WDTNumber Of I /o85
Program Memory Size64KB (22K x 24)Program Memory TypeFLASH
Ram Size8K x 8Voltage - Supply (vcc/vdd)3 V ~ 3.6 V
Data ConvertersA/D 32x10b/12bOscillator TypeInternal
Operating Temperature-40°C ~ 125°CPackage / Case100-TFQFP
For Use WithAC164333 - MODULE SKT FOR PM3 100QFPDM300024 - KIT DEMO DSPICDEM 1.1MA240012 - MODULE PLUG-IN PIC24H 100QFPDV164033 - KIT START EXPLORER 16 MPLAB ICD2DM240001 - BOARD DEMO PIC24/DSPIC33/PIC32Lead Free Status / RoHS StatusLead free / RoHS Compliant
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Page 32/84

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5.0
DEVICE PROGRAMMING – ICSP
Note:
Any development tool that modifies the con-
figuration memory on dsPIC33FJ06GS101/
102/202,
dsPIC33FJ16GS402/404/502/
504, dsPIC33FJ32GS406/606/608/610 and
dsPIC33FJ64GS406/606/608/610 devices
must take care to preserve the data con-
tained in the last six words of program mem-
ory. Refer to
Appendix C: “Diagnostic and
Calibration
Registers”
information.
ICSP mode is a special programming protocol that
allows you to read and write to dsPIC33F/PIC24H
device family memory. The ICSP mode is the most
direct method used to program the device; however,
note that Enhanced ICSP is faster. ICSP mode also
has the ability to read the contents of executive
memory to determine if the programming executive is
present. This capability is accomplished by applying
control codes and instructions serially to the device
using pins PGCx and PGDx.
In ICSP mode, the system clock is taken from the
PGCx pin, regardless of the device’s oscillator Config-
uration bits. All instructions are shifted serially into an
internal buffer, then loaded into the instruction register
and executed. No program fetching occurs from inter-
nal memory. Instructions are fed in 24 bits at a time.
PGDx is used to shift data in, and PGCx is used as both
the serial shift clock and the CPU execution clock.
Note:
During ICSP operation, the operating
frequency of PGCx must not exceed
5 MHz.
DS70152H-page 32
5.1
Overview of the Programming
Process
Figure 5-1
illustrates the high-level overview of the
programming process. After entering ICSP mode, the
first action is to Bulk Erase the device. Next, the code
memory is programmed, followed by the device
Configuration registers. Code memory (including the
Configuration registers) is then verified to ensure that
programming was successful. Then, program the
code-protect Configuration bits, if required.
for
more
FIGURE 5-1:
Program Configuration Bits
HIGH-LEVEL ICSP™
PROGRAMMING FLOW
Start
Enter ICSP™
Perform Bulk
Erase
Program Memory
Verify Program
Verify Configuration Bits
Exit ICSP
End
© 2010 Microchip Technology Inc.