PIC18F2431-I/SO Microchip Technology, PIC18F2431-I/SO Datasheet - Page 142

• Manufacturer Part Number: PIC18F2431-I/SO
• Description: IC PIC MCU FLASH 8KX16 28SOIC
• Manufacturer: Microchip Technology
• Series: PIC® 18Fr

Specifications of PIC18F2431-I/SO

• Program Memory Type: FLASH
• Program Memory Size: 16KB (8K x 16)
• Package / Case: 28-SOIC (7.5mm Width)
• Core Processor: PIC
• Core Size: 8-Bit
• Speed: 40MHz
• Connectivity: I²C, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, LVD, Power Control PWM, QEI, POR, PWM, WDT
• Number Of I /o: 24
• Eeprom Size: 256 x 8
• Ram Size: 768 x 8
• Voltage - Supply (vcc/vdd): 4.2 V ~ 5.5 V
• Data Converters: A/D 5x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Processor Series: PIC18F
• Core: PIC
• Data Bus Width: 8 bit
• Data Ram Size: 768 B
• Interface Type: EUSART/I2C/SPI/SSP
• Maximum Clock Frequency: 40 MHz
• Number Of Programmable I/os: 24
• Number Of Timers: 4
• Operating Supply Voltage: 2 V to 5.5 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: 52715-96, 52716-328, 52717-734, 52712-325, EWPIC18
• Development Tools By Supplier: PG164130, DV164035, DV244005, DV164005, PG164120, ICE2000, ICE4000, DM183021, DV164136
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 5-ch x 10-bit
• Package: 28SOIC W
• Device Core: PIC
• Family Name: PIC18
• Maximum Speed: 40 MHz
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: XLT28SO-1 - SOCKET TRANSITION 28SOIC 300MILI3-DB18F4431 - BOARD DAUGHTER ICEPIC3
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

PIC18F2331/2431/4331/4431
15.4
The Timer5 module includes an optional input noise
filter, designed to reduce spurious signals in noisy
operating environments. The filter ensures that the input
is not permitted to change until a stable value has been
registered for three consecutive sampling clock cycles.
The noise filter is part of the input filter network associ-
ated with the Motion Feedback Module (see
Section 17.0 “Motion Feedback
filters are controlled using the Digital Filter Control
(DFLTCON) register
can be individually enabled or disabled by setting or
clearing the FLT4EN bit (DFLTCON<6>). It is disabled
on all Brown-out Resets.
For additional information, refer to
“Noise Filters”
15.5
Timer5 has the ability to generate an interrupt on a
period match. When the PR5 register is loaded with a
new period value (00FFh), the Timer5 time base incre-
ments until its value is equal to the value of PR5. When
a match occurs, the Timer5 interrupt is generated on
the rising edge of Q4; TMR5IF is set on the next T
The interrupt latency (i.e., the time elapsed from the
moment Timer5 rolls over until TMR5IF is set) will not
exceed 1 T
and a TMR5/PR5 match occurs, the interrupt will be
generated on the first Q4 rising edge after TMR5 resets.
15.6
A Timer5 Special Event Trigger is generated on a
TMR5/PR5 match. The Special Event Trigger is
generated on the falling edge of Q3.
Timer5 must be configured for either Synchronous
mode (Counter or Timer) to take advantage of the
Special Event Trigger feature. If Timer5 is running in
Asynchronous Counter mode, the Special Event
Trigger may not work and should not be used.
15.7
In addition to the Special Event Trigger output, Timer5
has a Special Event Trigger Reset input that may be
used with Input Capture Channel 1 (IC1) of the Motion
Feedback Module. To use the Special Event Trigger
Reset, the Capture 1 Control register, CAP1CON, must
be configured for one of the Special Event Trigger
modes (CAP1M<3:0> = 1110 or 1111). The Special
Event Trigger Reset can be disabled by setting the
RESEN control bit (T5CON<6>).
The Special Event Trigger Reset resets the Timer5 time
base. This Reset occurs in either Continuous Count or
Single-Shot modes.
DS39616D-page 142
Noise Filter
Timer5 Interrupt
Timer5 Special Event Trigger
Output
Timer5 Special Event Trigger
Reset Input
CY
. When the Timer5 clock input is prescaled
in the Motion Feedback Module.
(Register
17-3). The Timer5 filter
Module”). All of the
Section 17.3
CY
.
15.7.1
The Timer5 Special Event Trigger Reset input can act
as a Timer5 wake-up and a start-up pulse. Timer5 must
be in Single-Shot mode and disabled (TMR5ON = 0).
An active edge on the CAP1 input pin will set TMR5ON.
The timer is subsequently incremented on the next fol-
lowing clock according to the prescaler and the Timer5
clock settings. A subsequent hardware time-out (such
as TMR5/PR5 match) will clear the TMR5ON bit and
stop the timer.
15.7.2
An active edge on CAP1 can also be used to initiate
some later action delayed by the Timer5 time base. In
this case, Timer5 increments as before after being
triggered. When the hardware time-out occurs, the
Special Event Trigger output is generated and used to
trigger another action, such as an A/D conversion. This
allows a given hardware action to be referenced from a
capture edge on CAP1 and delayed by the timer.
The event timing for the delayed action event trigger is
discussed further in
15.7.3
In the event that a bus write to Timer5 coincides with a
Special Event Trigger Reset, the bus write will always
take precedence over the Special Event Trigger Reset.
15.8
When Timer5 is configured for asynchronous operation,
it will continue to increment each timer clock (or prescale
multiple of clocks). Executing the SLEEP instruction will
either stop the timer or let the timer continue, depending
on the setting of the Timer5 Sleep Enable bit, T5SEN. If
T5SEN is set (= 1), the timer continues to run when the
SLEEP instruction is executed and the external clock is
selected (TMR5CS = 1). If T5SEN is cleared, the timer
stops when a SLEEP instruction is executed, regardless
of the state of the TMR5CS bit.
To summarize, Timer5 will continue to increment when
a SLEEP instruction is executed only if all of these bits
are set:
• TMR5ON
• T5SEN
• TMR5CS
• T5SYNC
15.8.1
When configured as described above, Timer5 will
continue to increment on each rising edge on T5CKI
while in Sleep mode. When a TMR5/PR5 match occurs,
an interrupt is generated which can wake the part.
Operation in Sleep Mode
WAKE-UP ON IC1 EDGE
DELAYED ACTION EVENT TRIGGER
SPECIAL EVENT TRIGGER RESET
WHILE TIMER5 IS INCREMENTING
INTERRUPT DETECT IN SLEEP MODE
Section 17.1 “Input
 2010 Microchip Technology Inc.
Capture”.