DSPIC33FJ256MC510T-I/PF Microchip Technology, DSPIC33FJ256MC510T-I/PF Datasheet - Page 173

• Manufacturer Part Number: DSPIC33FJ256MC510T-I/PF
• Description: IC DSPIC MCU/DSP 256K 100TQFP
• Manufacturer: Microchip Technology
• Series: dsPIC™ 33Fr

Specifications of DSPIC33FJ256MC510T-I/PF

• Core Processor: dsPIC
• Core Size: 16-Bit
• Speed: 40 MIPs
• Connectivity: CAN, I²C, IrDA, LIN, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, DMA, Motor Control PWM, QEI, POR, PWM, WDT
• Number Of I /o: 85
• Program Memory Size: 256KB (256K x 8)
• Program Memory Type: FLASH
• Ram Size: 16K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Data Converters: A/D 24x10b/12b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 100-TQFP, 100-VQFP
• For Use With: MA330013 - MODULE PLUG-IN DSPIC33 100TQFPDV164033 - KIT START EXPLORER 16 MPLAB ICD2DM240001 - BOARD DEMO PIC24/DSPIC33/PIC32AC164323 - MODULE SKT FOR 100TQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

14.0
The input capture module is useful in applications
requiring frequency (period) and pulse measurement.
The dsPIC33FJXXXMCX06/X08/X10 devices support
up to eight input capture channels.
The input capture module captures the 16-bit value of
the selected Time Base register when an event occurs
at the ICx pin. The events that cause a capture event
are listed below in three categories:
1.
FIGURE 14-1:
© 2009 Microchip Technology Inc.
Note:
Note: An ‘x’ in a signal, register or bit name denotes the number of the capture channel.
ICx Pin
Simple Capture Event modes
-Capture timer value on every falling edge of
-Capture timer value on every rising edge of
input at ICx pin
input at ICx pin
INPUT CAPTURE
This data sheet summarizes the features
of the dsPIC33FJXXXMCX06/X08/X10
family of devices. However, it is not
intended to be a comprehensive reference
source. To complement the information in
this data sheet, refer to Section 12.
“Input
“dsPIC33F Family Reference Manual”,
which is available from the Microchip web
site (www.microchip.com).
Prescaler
(1, 4, 16)
Counter
Capture”
3
INPUT CAPTURE BLOCK DIAGRAM
System Bus
ICxCON
ICM<2:0> (ICxCON<2:0>)
ICOV, ICBNE (ICxCON<4:3>)
Mode Select
(DS70198)
dsPIC33FJXXXMCX06/X08/X10
Edge Detection Logic
Clock Synchronizer
ICxI<1:0>
and
in
the
(in IFSn Register)
Set Flag ICxIF
Interrupt
Logic
2.
3.
Each input capture channel can select between one of
two 16-bit timers (Timer2 or Timer3) for the time base.
The selected timer can use either an internal or
external clock.
Other operational features include the following:
• Device wake-up from capture pin during CPU
• Interrupt on input capture event
• 4-word FIFO buffer for capture values
• Input capture can also be used to provide
Sleep and Idle modes
- Interrupt optionally generated after 1, 2, 3 or
additional sources of external interrupts
Note:
-Capture timer value on every 4th rising edge
-Capture timer value on every 16th rising
Capture timer value on every edge (rising and
falling) of input at ICx pin
Prescaler Capture Event modes
4 buffer locations are filled
of input at ICx pin
edge of input at ICx pin
Logic
FIFO
R/W
Only IC1 and IC2 can trigger a DMA data
transfer. If DMA data transfers are
required, the FIFO buffer size must be set
to ‘1’ (ICI<1:0> = 00).
From 16-bit Timers
TMRy TMRz
1
ICxBUF
16
0
DS70287C-page 171
16
ICTMR
(ICxCON<7>)