DSPIC33FJ256MC510T-I/PF Microchip Technology, DSPIC33FJ256MC510T-I/PF Datasheet - Page 25

• Manufacturer Part Number: DSPIC33FJ256MC510T-I/PF
• Description: IC DSPIC MCU/DSP 256K 100TQFP
• Manufacturer: Microchip Technology
• Series: dsPIC™ 33Fr

Specifications of DSPIC33FJ256MC510T-I/PF

• Core Processor: dsPIC
• Core Size: 16-Bit
• Speed: 40 MIPs
• Connectivity: CAN, I²C, IrDA, LIN, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, DMA, Motor Control PWM, QEI, POR, PWM, WDT
• Number Of I /o: 85
• Program Memory Size: 256KB (256K x 8)
• Program Memory Type: FLASH
• Ram Size: 16K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Data Converters: A/D 24x10b/12b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 100-TQFP, 100-VQFP
• For Use With: MA330013 - MODULE PLUG-IN DSPIC33 100TQFPDV164033 - KIT START EXPLORER 16 MPLAB ICD2DM240001 - BOARD DEMO PIC24/DSPIC33/PIC32AC164323 - MODULE SKT FOR 100TQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

3.0
The dsPIC33FJXXXMCX06/X08/X10 CPU module has
a 16-bit (data) modified Harvard architecture with an
enhanced instruction set, including significant support
for DSP. The CPU has a 24-bit instruction word with a
variable length opcode field. The Program Counter
(PC) is 23 bits wide and addresses up to 4M x 24 bits
of user program memory space. The actual amount of
program memory implemented varies by device. A sin-
gle-cycle instruction prefetch mechanism is used to
help maintain throughput and provides predictable exe-
cution. All instructions execute in a single cycle, with
the exception of instructions that change the program
flow, the double word move (MOV.D) instruction and the
table
constructs are supported using the DO and REPEAT
instructions, both of which are interruptible at any point.
The dsPIC33FJXXXMCX06/X08/X10 devices have
sixteen 16-bit working registers in the programmer’s
model. Each of the working registers can serve as a
data, address or address offset register. The 16th work-
ing register (W15) operates as a software Stack Pointer
(SP) for interrupts and calls.
The dsPIC33FJXXXMCX06/X08/X10 instruction set
has two classes of instructions: MCU and DSP. These
two instruction classes are seamlessly integrated into a
single CPU. The instruction set includes many
addressing modes and is designed for optimum C com-
piler
dsPIC33FJXXXMCX06/X08/X10 is capable of execut-
ing a data (or program data) memory read, a working
register (data) read, a data memory write and a pro-
gram (instruction) memory read per instruction cycle.
As a result, three parameter instructions can be sup-
ported, allowing A + B = C operations to be executed in
a single cycle.
A block diagram of the CPU is shown in Figure 3-1, and
the
dsPIC33FJXXXMCX06/X08/X10
Figure 3-2.
© 2009 Microchip Technology Inc.
Note:
instructions.
efficiency.
CPU
programmer’s
This data sheet summarizes the features
of the dsPIC33FJXXXMCX06/X08/X10
family of devices. However, it is not
intended to be a comprehensive reference
source. To complement the information in
this data sheet, refer to Section 2. “CPU”
(DS70204) in the “dsPIC33F Family
Reference Manual”, which is available
from
(www.microchip.com).
the
For
Overhead-free
most
Microchip
model
instructions,
is
dsPIC33FJXXXMCX06/X08/X10
program
web
shown
for
site
loop
the
the
in
3.1
The data space can be addressed as 32K words or
64 Kbytes and is split into two blocks referred to as X
and Y data memory. Each memory block has its own
independent Address Generation Unit (AGU). The
MCU class of instructions operates solely through the
X memory AGU, which accesses the entire memory
map as one linear data space. Certain DSP instructions
operate through the X and Y AGUs to support dual
operand reads, which splits the data address space
into two parts. The X and Y data space boundary is
device-specific.
Overhead-free circular buffers (Modulo Addressing
mode) are supported in both X and Y address spaces.
The Modulo Addressing removes the software bound-
ary checking overhead for DSP algorithms. Further-
more, the X AGU circular addressing can be used with
any of the MCU class of instructions. The X AGU also
supports Bit-Reversed Addressing to greatly simplify
input or output data reordering for radix-2 FFT algo-
rithms.
The upper 32 Kbytes of the data space memory map
can optionally be mapped into program space at any
16K program word boundary defined by the 8-bit Pro-
gram Space Visibility Page (PSVPAG) register. The
program to data space mapping feature lets any
instruction access program space as if it were data
space.
The data space also includes 2 Kbytes of DMA RAM,
which is primarily used for DMA data transfers but may
be used as general purpose RAM.
3.2
The DSP engine features a high-speed, 17-bit by 17-bit
multiplier, a 40-bit ALU, two 40-bit saturating accumu-
lators and a 40-bit bidirectional barrel shifter. The barrel
shifter is capable of shifting a 40-bit value up to 16 bits
right or left in a single cycle. The DSP instructions oper-
ate seamlessly with all other instructions and have
been designed for optimal real-time performance. The
MAC instruction and other associated instructions can
concurrently fetch two data operands from memory
while multiplying two W registers and accumulating and
optionally saturating the result in the same cycle. This
instruction functionality requires that the RAM memory
data space be split for these instructions and linear for
all others. Data space partitioning is achieved in a
transparent and flexible manner through dedicating
certain working registers to each address space.
Data Addressing Overview
DSP Engine Overview
DS70287C-page 23