PIC16LF84-04/SO Microchip Technology, PIC16LF84-04/SO Datasheet - Page 33

• Manufacturer Part Number: PIC16LF84-04/SO
• Description: IC MCU FLASH 1KX14 EE 18SOIC
• Manufacturer: Microchip Technology
• Series: PIC® 16Fr

Specifications of PIC16LF84-04/SO

• Core Size: 8-Bit
• Program Memory Size: 1.75KB (1K x 14)
• Core Processor: PIC
• Speed: 4MHz
• Peripherals: POR, WDT
• Number Of I /o: 13
• Program Memory Type: FLASH
• Eeprom Size: 64 x 8
• Ram Size: 68 x 8
• Voltage - Supply (vcc/vdd): 2 V ~ 6 V
• Oscillator Type: External
• Operating Temperature: 0°C ~ 70°C
• Package / Case: 18-SOIC (7.5mm Width)
• Controller Family/series: PIC16LF
• No. Of I/o's: 13
• Eeprom Memory Size: 64Byte
• Ram Memory Size: 68Byte
• Cpu Speed: 4MHz
• No. Of Timers: 1
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Data Converters: -
• Connectivity: -
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Lead free / RoHS Compliant
• Other names: PIC16LC84A-04/SO

7.0
The EEPROM data memory is readable and writable
during normal operation (full V
is not directly mapped in the register file space. Instead
it is indirectly addressed through the Special Function
Registers. There are four SFRs used to read and write
this memory. These registers are:
• EECON1
• EECON2
• EEDATA
• EEADR
EEDATA holds the 8-bit data for read/write, and EEADR
holds the address of the EEPROM location being
accessed. PIC16F8X devices have 64 bytes of data
EEPROM with an address range from 0h to 3Fh.
The EEPROM data memory allows byte read and write.
A byte write automatically erases the location and
writes the new data (erase before write). The EEPROM
FIGURE 7-1:
1998 Microchip Technology Inc.
bit 7:5
bit 4
bit 3
bit 2
bit 1
bit 0
bit7
—
U
DATA EEPROM MEMORY
Unimplemented: Read as ’0’
EEIF: EEPROM Write Operation Interrupt Flag bit
1 = The write operation completed (must be cleared in software)
0 = The write operation is not complete or has not been started
WRERR: EEPROM Error Flag bit
1 = A write operation is prematurely terminated
0 = The write operation completed
WREN: EEPROM Write Enable bit
1 = Allows write cycles
0 = Inhibits write to the data EEPROM
WR: Write Control bit
1 = initiates a write cycle. (The bit is cleared by hardware once write is complete. The WR bit can only
0 = Write cycle to the data EEPROM is complete
RD: Read Control bit
1 = Initiates an EEPROM read (read takes one cycle. RD is cleared in hardware. The RD bit can only
0 = Does not initiate an EEPROM read
—
U
(any MCLR reset or any WDT reset during normal operation)
be set (not cleared) in software.
be set (not cleared) in software).
EECON1 REGISTER (ADDRESS 88h)
—
U
DD
range). This memory
R/W-0
EEIF
WRERR
R/W-x
WREN
R/W-0
data memory is rated for high erase/write cycles. The
write time is controlled by an on-chip timer. The write-
time will vary with voltage and temperature as well as
from chip to chip. Please refer to AC specifications for
exact limits.
When the device is code protected, the CPU may
continue to read and write the data EEPROM memory.
The device programmer can no longer access
this memory.
7.1
The EEADR register can address up to a maximum of
256 bytes of data EEPROM. Only the first 64 bytes of
data EEPROM are implemented.
The upper two bits are address decoded. This means
that these two bits must always be '0' to ensure that the
address is in the 64 byte memory space.
R/S-0
WR
EEADR
R/S-x
RD
bit0
R = Readable bit
W = Writable bit
S = Settable bit
U = Unimplemented bit,
- n = Value at POR reset
read as ‘0’
PIC16F8X
DS30430C-page 33