DSPIC33FJ64GP310-E/PF Microchip Technology, DSPIC33FJ64GP310-E/PF Datasheet - Page 107

• Manufacturer Part Number: DSPIC33FJ64GP310-E/PF
• Description: IC DSPIC MCU/DSP 64K 100TQFP
• Manufacturer: Microchip Technology
• Series: dsPIC™ 33Fr

Specifications of DSPIC33FJ64GP310-E/PF

• Core Processor: dsPIC
• Core Size: 16-Bit
• Speed: 40 MIPs
• Connectivity: I²C, IrDA, LIN, SPI, UART/USART
• Peripherals: AC'97, Brown-out Detect/Reset, DMA, I²S, POR, PWM, WDT
• Number Of I /o: 85
• Program Memory Size: 64KB (64K x 8)
• Program Memory Type: FLASH
• Ram Size: 16K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Data Converters: A/D 32x10b/12b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 125°C
• Package / Case: 100-TQFP, 100-VQFP
• For Use With: DM300024 - KIT DEMO DSPICDEM 1.1DV164033 - KIT START EXPLORER 16 MPLAB ICD2MA330012 - MODULE DSPIC33 100P TO 84QFPMA330011 - MODULE DSPIC33 100P TO 100QFPDM240001 - BOARD DEMO PIC24/DSPIC33/PIC32AC164323 - MODULE SKT FOR 100TQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

REGISTER 7-14:
© 2009 Microchip Technology Inc.
bit 15
bit 7
Legend:
R = Readable bit
-n = Value at POR
bit 15-8
bit 7
bit 6
bit 5
bit 4
bit 3
bit 2
bit 1
bit 0
C2TXIE
R/W-0
U-0
—
Unimplemented: Read as ‘0’
C2TXIE: ECAN2 Transmit Data Request Interrupt Enable bit
1 = Interrupt request enabled
0 = Interrupt request not enabled
C1TXIE: ECAN1 Transmit Data Request Interrupt Enable bit
1 = Interrupt request enabled
0 = Interrupt request not enabled
DMA7IE: DMA Channel 7 Data Transfer Complete Enable Status bit
1 = Interrupt request enabled
0 = Interrupt request not enabled
DMA6IE: DMA Channel 6 Data Transfer Complete Enable Status bit
1 = Interrupt request enabled
0 = Interrupt request not enabled
Unimplemented: Read as ‘0’
U2EIE: UART2 Error Interrupt Enable bit
1 = Interrupt request enabled
0 = Interrupt request not enabled
U1EIE: UART1 Error Interrupt Enable bit
1 = Interrupt request enabled
0 = Interrupt request not enabled
Unimplemented: Read as ‘0’
C1TXIE
R/W-0
U-0
—
IEC4: INTERRUPT ENABLE CONTROL REGISTER 4
W = Writable bit
‘1’ = Bit is set
DMA7IE
R/W-0
U-0
—
dsPIC33FJXXXGPX06/X08/X10
DMA6IE
R/W-0
U-0
—
‘0’ = Bit is cleared
U = Unimplemented bit, read as ‘0’
U-0
U-0
—
—
U2EIE
R/W-0
U-0
—
x = Bit is unknown
U1EIE
R/W-0
U-0
—
DS70286C-page 105
U-0
U-0
—
—
bit 8
bit 0