AT32UC3A364-CTUR Atmel, AT32UC3A364-CTUR Datasheet - Page 73

• Manufacturer Part Number: AT32UC3A364-CTUR
• Description: IC MCU 64KB FLASH 144TBGA
• Manufacturer: Atmel
• Series: AVR®32 UC3r

Specifications of AT32UC3A364-CTUR

• Package / Case: 144-TBGA
• Voltage - Supply (vcc/vdd): 1.65 V ~ 1.95 V
• Operating Temperature: -40°C ~ 85°C
• Speed: 66MHz
• Number Of I /o: 110
• Core Processor: AVR
• Program Memory Type: FLASH
• Ram Size: 128K x 8
• Program Memory Size: 64KB (64K x 8)
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Peripherals: Brown-out Detect/Reset, DMA, POR, WDT
• Connectivity: EBI/EMI, I²C, IrDA, MMC, SPI, SSC, UART/USART, USB OTG
• Core Size: 32-Bit
• Processor Series: AT32UC3x
• Core: AVR32
• Data Bus Width: 32 bit
• Data Ram Size: 64 KB
• Interface Type: 2-Wire, I2S, JTAG, SPI, USART
• Maximum Clock Frequency: 66 MHz
• Number Of Programmable I/os: 23
• Number Of Timers: 4
• Operating Supply Voltage: - 0.3 V to + 3.6 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: EWAVR32, EWAVR32-BL, KSK-EVK1100-PL
• Development Tools By Supplier: ATAVRDRAGON, ATSTK500, ATSTK600, ATAVRISP2, ATAVRONEKIT, ATEXTWIFI, ATEVK1104
• Minimum Operating Temperature: - 40 C
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Details

Table of Contents
1
2
3
4
5
6
7
8
9
32072AS–AVR32–03/09
Features ..................................................................................................... 1
Description ............................................................................................... 3
Blockdiagram ........................................................................................... 4
Signals Description .................................................................................. 6
Package and Pinout ............................................................................... 11
Power Considerations ........................................................................... 23
I/O Line Considerations ......................................................................... 24
Memories ................................................................................................ 25
Peripherals .............................................................................................. 29
Boot Sequence ....................................................................................... 43
2.1Processor and Architecture .......................................................................................5
4.1Package ...................................................................................................................11
4.2Peripheral Multiplexing on I/O lines .........................................................................13
4.3Signal Descriptions ..................................................................................................17
4.4Power Considerations .............................................................................................22
5.1Power Supplies ........................................................................................................23
5.2Voltage Regulator ....................................................................................................23
6.1JTAG Pins ...............................................................................................................24
6.2RESET_N Pin ..........................................................................................................24
6.3TWI Pins ..................................................................................................................24
6.4GPIO Pins ................................................................................................................24
7.1Embedded Memories ..............................................................................................25
7.2Physical Memory Map .............................................................................................25
7.3Peripheral Address Map ..........................................................................................26
7.4CPU Local Bus Mapping .........................................................................................28
8.1Clock Connections ...................................................................................................29
8.2Peripheral Multiplexing on I/O lines .........................................................................29
8.3Oscillator Pinout ......................................................................................................32
8.4Peripheral overview .................................................................................................34
9.1Starting of Clocks ....................................................................................................43
9.2Fetching of Initial Instructions ..................................................................................43
AT32UC3A3
i