DSPIC33FJ64GS608-I/PT Microchip Technology, DSPIC33FJ64GS608-I/PT Datasheet - Page 230

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DSPIC33FJ64GS608-I/PT

Manufacturer Part Number
DSPIC33FJ64GS608-I/PT
Description
IC MCU/DSP 64KB FLASH 80TQFP
Manufacturer
Microchip Technology
Series
dsPIC™ 33Fr

Specifications of DSPIC33FJ64GS608-I/PT

Program Memory Type
FLASH
Program Memory Size
64KB (64K x 8)
Package / Case
80-TFQFP
Core Processor
dsPIC
Core Size
16-Bit
Speed
40 MIPs
Connectivity
CAN, I²C, IrDA, LIN, SPI, UART/USART, USB
Peripherals
Brown-out Detect/Reset, DMA, QEI, POR, PWM, WDT
Number Of I /o
74
Ram Size
9K x 8
Voltage - Supply (vcc/vdd)
3 V ~ 3.6 V
Data Converters
A/D 18x10b, D/A 1x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Product
DSCs
Data Bus Width
16 bit
Processor Series
DSPIC33F
Core
dsPIC
Numeric And Arithmetic Format
Fixed-Point or Floating-Point
Instruction Set Architecture
Harvard
Device Million Instructions Per Second
40 MIPs
Maximum Clock Frequency
120 MHz
Number Of Programmable I/os
74
Data Ram Size
4 KB
Operating Supply Voltage
3.3 V
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
3rd Party Development Tools
52713-733, 52714-737, 53276-922, EWDSPIC
Development Tools By Supplier
PG164130, DV164035, DV244005, DV164005, PG164120, DM240001, DV164033
Interface Type
I2C, SPI, UART
Minimum Operating Temperature
- 40 C
On-chip Adc
10 bit, 18 Channel
On-chip Dac
10 bit, 4 Channel
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Lead Free Status / Rohs Status
Lead free / RoHS Compliant

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DSPIC33FJ64GS608-I/PT
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DSPIC33FJ64GS608-I/PT
0
dsPIC33FJ32GS406/606/608/610 and dsPIC33FJ64GS406/606/608/610
REGISTER 16-1:
DS70591C-page 230
bit 3-0
Note 1: These bits should be changed only when PTEN = 0. In addition, when using the SYNCIx feature, the user
application must program the period register with a value that is slightly larger than the expected period of
the external synchronization input signal.
SEVTPS<3:0>: PWM Special Event Trigger Output Postscaler Select bits
1111 = 1:16 Postscaler generates Special Event Trigger on every sixteenth compare match event
0001 = 1:2 Postscaler generates Special Event Trigger on every second compare match event
0000 = 1:1 Postscaler generates Special Event Trigger on every compare match event
PTCON: PWM TIME BASE CONTROL REGISTER (CONTINUED)
Preliminary
 2010 Microchip Technology Inc.
(1)

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