DSPIC33FJ64GS608-I/PT Microchip Technology, DSPIC33FJ64GS608-I/PT Datasheet - Page 239

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DSPIC33FJ64GS608-I/PT

Manufacturer Part Number
DSPIC33FJ64GS608-I/PT
Description
IC MCU/DSP 64KB FLASH 80TQFP
Manufacturer
Microchip Technology
Series
dsPIC™ 33Fr

Specifications of DSPIC33FJ64GS608-I/PT

Program Memory Type
FLASH
Program Memory Size
64KB (64K x 8)
Package / Case
80-TFQFP
Core Processor
dsPIC
Core Size
16-Bit
Speed
40 MIPs
Connectivity
CAN, I²C, IrDA, LIN, SPI, UART/USART, USB
Peripherals
Brown-out Detect/Reset, DMA, QEI, POR, PWM, WDT
Number Of I /o
74
Ram Size
9K x 8
Voltage - Supply (vcc/vdd)
3 V ~ 3.6 V
Data Converters
A/D 18x10b, D/A 1x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Product
DSCs
Data Bus Width
16 bit
Processor Series
DSPIC33F
Core
dsPIC
Numeric And Arithmetic Format
Fixed-Point or Floating-Point
Instruction Set Architecture
Harvard
Device Million Instructions Per Second
40 MIPs
Maximum Clock Frequency
120 MHz
Number Of Programmable I/os
74
Data Ram Size
4 KB
Operating Supply Voltage
3.3 V
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
3rd Party Development Tools
52713-733, 52714-737, 53276-922, EWDSPIC
Development Tools By Supplier
PG164130, DV164035, DV244005, DV164005, PG164120, DM240001, DV164033
Interface Type
I2C, SPI, UART
Minimum Operating Temperature
- 40 C
On-chip Adc
10 bit, 18 Channel
On-chip Dac
10 bit, 4 Channel
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Lead Free Status / Rohs Status
Lead free / RoHS Compliant

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0
REGISTER 16-12: PDCx: PWM GENERATOR DUTY CYCLE REGISTER
REGISTER 16-13: SDCx: PWM SECONDARY DUTY CYCLE REGISTER
 2010 Microchip Technology Inc.
bit 15
bit 7
Legend:
R = Readable bit
-n = Value at POR
bit 15-0
bit 15
bit 7
Legend:
R = Readable bit
-n = Value at POR
bit 15-0
dsPIC33FJ32GS406/606/608/610 and dsPIC33FJ64GS406/606/608/610
Note 1: In Independent PWM mode, the PDCx register controls the PWMxH duty cycle only. In
Note 1: The SDCx register is used in Independent PWM mode only. When used in Independent PWM mode, the
R/W-0
R/W-0
R/W-0
R/W-0
2: The smallest pulse width that can be generated on the PWM output corresponds to a value of 0x0008,
3: As the Duty Cycle gets closer to 0% or 100% of the PWM Period (0 to 40 ns, depending on the mode of
2: The smallest pulse width that can be generated on the PWM output corresponds to a value of 0x0008,
3: As the Duty Cycle gets closer to 0% or 100% of the PWM Period (0 to 40 ns, depending on the mode of
the Complementary, Redundant and Push-Pull PWM modes, the PDCx register controls the duty cycle of
both the PWMxH and PWMxL.
while the maximum pulse width generated corresponds to a value of Period - 0x0008.
operation), PWM Duty Cycle resolution will increase from 1 to 3 LSBs.
SDCx register controls the PWMxL duty cycle.
while the maximum pulse width generated corresponds to a value of Period - 0x0008.
operation), PWM Duty Cycle resolution will increase from 1 to 3 LSBs.
PDCx<15:0>: PWM Generator # Duty Cycle Value bits
SDCx<15:0>: Secondary Duty Cycle bits for PWMxL Output Pin
R/W-0
R/W-0
R/W-0
R/W-0
W = Writable bit
‘1’ = Bit is set
W = Writable bit
‘1’ = Bit is set
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
Preliminary
PDCx<15:8>
SDCx<15:8>
PDCx<7:0>
SDCx<7:0>
U = Unimplemented bit, read as ‘0’
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared
‘0’ = Bit is cleared
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
x = Bit is unknown
x = Bit is unknown
R/W-0
R/W-0
R/W-0
R/W-0
DS70591C-page 239
R/W-0
R/W-0
R/W-0
R/W-0
bit 8
bit 0
bit 8
bit 0

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