AT32UC3A3128-CTUT Atmel, AT32UC3A3128-CTUT Datasheet
AT32UC3A3128-CTUT
Specifications of AT32UC3A3128-CTUT
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AT32UC3A3128-CTUT Summary of contents
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... Memory Stick: Standard Format V1.40, PRO Format V1.00, Micro – IDE Interface • One Advanced Encryption System (AES) for AT32UC3A3256S, AT32UC3A3128S, AT32UC3A364S, AT32UC3A4256S, AT32UC3A4128S and AT32UC3A364S – 256-, 192-, 128-bit Key Algorithm, Compliant with FIPS PUB 197 Specifications – Buffer Encryption/Decryption Capabilities • ...
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Support for SPI and LIN – Optionnal support for IrDA, ISO7816, Hardware Handshaking, RS485 interfaces and Modem Line • Two Master/Slave Serial Peripheral Interfaces (SPI) with Chip Select Signals • One Synchronous Serial Protocol Controller – Supports I2S and ...
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Description The AT32UC3A3/ complete System-On-Chip microcontroller based on the AVR32 UC RISC processor running at frequencies up to 66MHz. AVR32 high-performance 32-bit RISC microprocessor core, designed for cost-sensitive embedded applications, with particular emphasis on ...
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Blockdiagram Figure 2-1. Blockdiagram TCK JTAG TDO INTERFACE TDI TMS MCKO MDO[5..0] MSEO[1..0] EVTI_N EVTO_N USB_VBIAS USB_VBUS USB HS DMFS, DMHS DPFS, DPHS INTERFACE ID VBOF DMA 32KB RAM 32KB RAM DMACA AES CLK CMD[1..0] DATA[15.. ...
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Processor and Architecture 2.1.1 AVR32 UC CPU • 32-bit load/store AVR32A RISC architecture – 15 general-purpose 32-bit registers – 32-bit Stack Pointer, Program Counter and Link Register reside in register file – Fully orthogonal instruction set – Privileged and ...
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Signals Description The following table gives details on the signal name classified by peripheral Table 3-1. Signal Description List Signal Name Function VDDIO I/O Power Supply VDDANA Analog Power Supply VDDIN Voltage Regulator Input Supply ONREG Voltage Regulator ON/OFF ...
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Table 3-1. Signal Description List Signal Name Function GCLK[2:0] Generic Clock Pins RESET_N Reset Pin DMAACK[1:0] DMA Acknowledge DMARQ[1:0] DMA Requests EXTINT[7:0] External Interrupt Pins KPS0 - KPS7 Keypad Scan Pins NMI_N Non-Maskable Interrupt Pin General Purpose Input/Output pin - ...
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Table 3-1. Signal Description List Signal Name Function RAS Row Signal SDA10 SDRAM Address 10 Line SDCK SDRAM Clock SDCKE SDRAM Clock Enable SDCS SDRAM Chip Select SDWE SDRAM Write Enable CLK Multimedia Card Clock CMD[1:0] Multimedia Card Command DATA[15:0] ...
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Table 3-1. Signal Description List Signal Name Function B2 Channel 2 Line B CLK0 Channel 0 External Clock Input CLK1 Channel 1 External Clock Input CLK2 Channel 2 External Clock Input SCL Serial Clock SDA Serial Data Universal Synchronous Asynchronous ...
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Table 3-1. Signal Description List Signal Name Function HSDP USB High Speed Data + USB_VBIAS USB VBIAS reference USB_VBUS USB VBUS for OTG feature 32072C–AVR32–2010/03 AT32UC3A3/A4 Active Type Level Comments Analog Connect to the ground through a Analog 6810ohms (+/- ...
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Package and Pinout 4.1 Package The device pins are multiplexed with peripheral functions as described in the Peripheral Multi- plexing on I/O Line section. Figure 4-1. TFBGA144 Pinout (top view) Table 4-1. TFBGA144 Package Pinout ...
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Figure 4-2. LQFP144 Pinout Table 4-2. LQFP144 Package Pinout 1 USB_VBUS 25 PB02 2 VDDIO 26 PA27 3 USB_VBIAS 27 PB01 4 GNDIO 28 PA28 5 DMHS 29 PA31 6 DPHS 30 PB00 7 GNDIO 31 PB11 8 DMFS 32 ...
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Figure 4-3. VFBGA100 Pinout (top view) Table 4-3. VFBGA100 Package Pinout PA28 PA27 PB04 B PB00 PB01 PB02 C PB11 PA31 GNDIO D PX12 PX10 PX13 E (1) GNDIO PX08 PA02/PX47 F (1) VDDIO PX06 PX19/PX59 ...
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Peripheral Multiplexing on I/O lines Each GPIO line can be assigned to one of 4 peripheral functions The following table defines how the I/O lines on the peripherals are ...
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Table 4-4. GPIO Controller Function Multiplexing PB02 PB03 PB04 (1) H12 121 F7 PB05 D12 134 D7 PB06 D11 135 D6 PB07 PB08 PB09 D7 ...
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Table 4-4. GPIO Controller Function Multiplexing PX23 PX24 PX25 PX26 PX27 L10 91 K3 PX28 K11 94 J4 PX29 M11 96 G5 PX30 M10 97 ...
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Oscillator Pinout Table 4-5. Oscillator Pinout TFBGA144 QFP144 Note: 4.2.2 JTAG port connections Table 4-6. JTAG Pinout TFBGA144 QFP144 K12 L12 J11 J10 4.2.3 Nexus OCD AUX port connections If the OCD trace ...
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Signal Descriptions The following table gives details on signal name classified by peripheral. Table 4-8. Signal Description List Signal Name Function VDDIO I/O Power Supply VDDANA Analog Power Supply VDDIN Voltage Regulator Input Supply VDDCORE Voltage Regulator Output for ...
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Table 4-8. Signal Description List Signal Name Function RESET_N Reset Pin DMAACK[1:0] DMA Acknowledge DMARQ[1:0] DMA Requests EXTINT[7:0] External Interrupt Pins SCAN[7:0] Keypad Scan Pins NMI Non-Maskable Interrupt Pin General Purpose Input/Output pin - GPIOA, GPIOB, GPIOC, GPIOX PA[31:0] Parallel ...
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Table 4-8. Signal Description List Signal Name Function SDA10 SDRAM Address 10 Line SDCK SDRAM Clock SDCKE SDRAM Clock Enable SDWE SDRAM Write Enable CLK Multimedia Card Clock CMD[1:0] Multimedia Card Command DATA[15:0] Multimedia Card Data SCLK Memory Stick Clock ...
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Table 4-8. Signal Description List Signal Name Function B0 Channel 0 Line B B1 Channel 1 Line B B2 Channel 2 Line B CLK0 Channel 0 External Clock Input CLK1 Channel 1 External Clock Input CLK2 Channel 2 External Clock ...
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Table 4-8. Signal Description List Signal Name Function DMHS USB High Speed Data - DPHS USB High Speed Data + USB_VBIAS USB VBIAS reference USB_VBUS USB VBUS for OTG feature VBOF USB VBUS on/off bus power control port ID ID ...
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I/O Line Considerations 4.4.1 JTAG Pins TMS and TDI pins have pull-up resistors. TDO pin is an output, driven VDDIO, and has no pull-up resistor. 4.4.2 RESET_N Pin The RESET_N pin is a schmitt input and ...
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Power Considerations 4.5.1 Power Supplies The AT32UC3A3 has several types of power supply pins: • VDDIO: Powers I/O lines. Voltage is 3.3V nominal • VDDANA: Powers the ADC. Voltage is 3.3V nominal • VDDIN: Input voltage for the voltage ...
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Power Considerations 5.1 Power Supplies The AT32UC3A3/A4 has several types of power supply pins: • VDDIO: Powers I/O lines. Voltage is 3.3V nominal • VDDANA: Powers the ADC Voltage and provides the ADVREF voltage is 3.3V nominal • VDDIN: ...
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I/O Line Considerations 6.1 JTAG Pins TMS and TDI pins have pull-up resistors. TDO pin is an output, driven VDDIO, and has no pull-up resistor. 6.2 RESET_N Pin The RESET_N pin is a schmitt input and ...
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... Memories 7.1 Embedded Memories • Internal High-Speed Flash – 256KBytes (AT32UC3A3256/S) – 128Kbytes (AT32UC3A3128/S) – 64Kbytes (AT32UC3A364/S) • Internal High-Speed SRAM – 64KBytes, Single-cycle access at full speed on CPU Local Bus and accessible through the High Speed Bud (HSB) matrix – 2x32KBytes, accessible independently through the High Speed Bud (HSB) matrix 7 ...
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... Bus Monitor module - BUSMON MCI Mulitmedia Card Interface - MCI MSI Memory Stick Interface - MSI PDCA Peripheral DMA Controller - PDCA INTC Interrupt controller - INTC AT32UC3A3/A4 Size Size AT32UC3A3128S AT32UC3A364S AT32UC3A3128 AT32UC3A364 AT32UC3A4128S AT32UC3A464S AT32UC3A4128 AT32UC3A464 32KByte 32KByte 32KByte 32KByte 64KByte 64KByte 64KByte 64KByte ...
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Table 7-2. Peripheral Address Mapping 0xFFFF0C00 0xFFFF0D00 0xFFFF0D30 0xFFFF0D80 0xFFFF1000 0xFFFF1400 0xFFFF1800 0xFFFF1C00 0xFFFF2000 0xFFFF2400 0xFFFF2800 0xFFFF2C00 0xFFFF3000 0xFFFF3400 0xFFFF3800 0xFFFF3C00 0xFFFF4000 0xFFFF4400 32072C–AVR32–2010/03 PM Power Manager - PM RTC Real Time Counter - RTC WDT Watchdog Timer - WDT ...
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Table 7-2. Peripheral Address Mapping 0xFFFF5000 0xFFFF5400 7.4 CPU Local Bus Mapping Some of the registers in the GPIO module are mapped onto the CPU local bus, in addition to being mapped on the Peripheral Bus. These registers can therefore ...
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Table 7-3. Port 2 3 32072C–AVR32–2010/03 Local Bus Mapped GPIO Registers Register Output Driver Enable Register (ODER) Output Value Register (OVR) Pin Value Register (PVR) Output Driver Enable Register (ODER) Output Value Register (OVR) Pin Value Register (PVR) AT32UC3A3/A4 Local ...
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Peripherals 8.1 Clock Connections 8.1.1 Timer/Counters Each Timer/Counter channel can independently select an internal or external clock source for its counter: Table 8-1. Source Internal External 8.2 Peripheral Multiplexing on I/O lines Each GPIO line can be assigned to ...
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Table 8-2. GPIO Controller Function Multiplexing J6 100 PA14 J7 101 PA15 F12 128 PA16 H7 116 PA17 K8 115 PA18 J8 114 PA19 J9 113 PA20 H9 109 PA21 H10 110 PA22 G8 111 PA23 G9 112 PA24 E9 ...
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Table 8-2. GPIO Controller Function Multiplexing H6 99 PC01 A7 18 PC02 B7 19 PC03 A8 13 PC04 A9 12 PC05 G1 55 PX00 H1 59 PX01 J2 62 PX02 K1 63 PX03 J1 60 PX04 G2 58 PX05 F3 ...
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Table 8-2. GPIO Controller Function Multiplexing K11 94 PX29 M11 96 PX30 M10 97 PX31 M9 93 PX32 M12 95 PX33 J3 61 PX34 C2 38 PX35 D3 44 PX36 D2 45 PX37 E1 51 PX38 F1 52 PX39 A1 ...
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Table 8-3. 32072C–AVR32–2010/03 Oscillator Pinout AT32UC3A3/A4 PC00 xin32 PC03 xout0 PC05 xout1 PC01 xout32 36 ...
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Peripheral overview 8.4.1 Power Manager • Controls integrated oscillators and PLLs • Generates clocks and resets for digital logic • Supports 2 crystal oscillators 0.4-20MHz • Supports 2 PLLs 40-240MHz • Supports 32KHz ultra-low power oscillator • Integrated low-power ...
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groups of interrupts with interrupt requests in each group 8.4.5 External Interrupts Controller • Dedicated interrupt request for each interrupt • Individually maskable interrupts • Interrupt on rising or falling edge • Interrupt ...
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One Cycle Latency for the First Access of a Burst • Zero Cycle Latency for Default Master • One Special Function Register for Each Slave (Not dedicated) 8.4.8 External Bus Interface • Optimized for application memory space support • ...
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Timing parameters specified by software – Automatic refresh operation, refresh rate is programmable – Automatic update of DS, TCR and PASR parameters (mobile SDRAM devices) • Energy-saving capabilities – Self-refresh, power-down, and deep power-down modes supported – Supports mobile ...
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Serial memories, such as DataFlash and 3-wire EEPROMs – Serial peripherals, such as ADCs, DACs, LCD controllers, CAN controllers and Sensors – External co-processors • Master or Slave Serial Peripheral Bus Interface – 16-bit programmable data ...
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... Compatible with PMBus • Compatible with Atmel Two-Wire Interface Serial Memories • DMA interface for reducing CPU load • Arbitrary transfer lengths, including 0 data bytes • Optional clock stretching if transmit or receive buffers not ready for data transfer 8.4.16 Synchronous Serial Controller • ...
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Full LIN error checking and reporting – Frame Slot Mode: the Master allocates slots to the scheduled frames automatically. – Generation of the Wakeup signal • Test Modes – Remote Loopback, Local Loopback, Automatic Echo • Supports Connection of ...
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HSB Bus Performance Monitor • Allows performance monitoring of High Speed Bus master interfaces – masters can be monitored – Peripheral Bus access to monitor registers • The following is monitored – Data transfer cycles – ...
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Advanced Encryption Standart • Compliant with FIPS Publication 197, Advanced Encryption Standard (AES) • 128-bit/192-bit/256-bit cryptographic key • 12/14/16 clock cycles encryption/decryption processing time with a 128-bit/192-bit/256-bit cryptographic key • Support of the five standard modes of operation specified ...
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Boot Sequence This chapter summarizes the boot sequence of the AT32UC3A3/A4. The behavior after power controlled by the Power Manager. For specific details, refer to (PM)” on page 9.1 Starting of Clocks After power-up, the device will ...
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Electrical Characteristics 10.1 Absolute Maximum Ratings* Operating Temperature.................................... -40°C to +85°C Storage Temperature ..................................... -60°C to +150°C Voltage on Input Pin with respect to Ground ........................................-0.3V to 3.6V Maximum Operating Voltage (VDDCORE) ..................... 1.95V Maximum Operating Voltage (VDDIO).............................. 3.6V ...
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Table 10-2. Pins Drive Capabilities PIN Drive PIN PA00 3x PA22 PA01 1x PA23 PA02 1x PA24 PA03 1x PA25 PA04 1x PA26 PA05 1x PA27 PA06 1x PA28 PA07 1x PA29 PA08 3x PA30 PA09 2x PA31 PA10 2x ...
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Regulator characteristics Table 10-3. Electrical Characteristics Symbol Parameter V Supply voltage (input) VDDIN V Supply voltage (output) VDDCORE Table 10-4. Decoupling Requirements Symbol Parameter C Input Regulator Capacitor 1 IN1 C Input Regulator Capacitor 2 IN2 C Output Regulator ...
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Reset Sequence Table 10-9. Electrical Characteristics Symbol Parameter VDDCORE rise rate to ensure power- V DDRR on-reset VDDCORE fall rate to ensure power- V DDFR on-reset Rising threshold voltage: voltage which device is kept under reset ...
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Figure 10-1. MCU Cold Start-Up RESET_N tied to VDDIN VDDCORE RESET_N Internal POR Reset Internal MCU Reset Figure 10-2. MCU Cold Start-Up RESET_N Externally Driven VDDCORE RESET_N Internal POR Reset Internal MCU Reset Figure 10-3. MCU Hot Start-Up VDDCORE RESET_N ...
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RESET_N Characteristics Table 10-10. RESET_N Waveform Parameters Symbol Parameter t RESET_N minimum pulse width RESET 32072C–AVR32–2010/03 Conditions AT32UC3A3/A4 Min. Typ. Max. Unit ...
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Power Consumption The values in sumption with operating conditions as follows: •V DDIO •T = 25°C A •I/Os are configured in input, pull-up enabled. Figure 10-4. Measurement Setup 32072C–AVR32–2010/03 Table 10-11 and Table 10-12 on page 54 = 3.3V ...
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These figures represent the power consumption measured on the power supplies. Table 10-11. Power Consumption for Different Modes Mode Active Static 1. Table 10-12. Power Consumption by Peripheral in Active Mode Peripheral GPIO SMC SDRAMC ADC EBI INTC TWI PDCA ...
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System Clock Characteristics These parameters are given in the following conditions: • V DDCORE • Ambient Temperature = 25°C 10.6.1 CPU/HSB Clock Characteristics Table 10-13. Core Clock Waveform Parameters Symbol Parameter 1/(t ) CPU Clock Frequency CPCPU t CPU ...
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Oscillator Characteristics The following characteristics are applicable to the operating temperature range: T power supply, unless otherwise specified. 10.7.1 Slow Clock RC Oscillator Table 10-16. RC Oscillator Frequency Symbol Parameter F RC Oscillator Frequency RC 10.7.2 32 KHz Oscillator ...
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Main Oscillators Table 10-18. Main Oscillators Characteristics Symbol Parameter 1/(t ) Oscillator Frequency CPMAIN Internal Load Capacitance ( ESR Crystal Equivalent Series Resistance Duty Cycle t Startup Time ST t XIN Clock High Half-period ...
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ADC Characteristics Table 10-20. Channel Conversion Time and ADC Clock Parameter ADC Clock Frequency Startup Time Track and Hold Acquisition Time Conversion Time Throughput Rate 1. Corresponds to 13 clock cycles: 3 clock cycles for track and hold acquisition ...
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Table 10-24. Transfer Characteristics in 10-bit mode Parameter Differential Non-linearity Offset Error Gain Error 32072C–AVR32–2010/03 Conditions ADC Clock = 5 MHz ADC Clock = 2.5 MHz ADC Clock = 5 MHz ADC Clock = 5 MHz AT32UC3A3/A4 Min. Typ. Max. ...
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USB Transceiver Characteristics 10.9.1 Electrical Characteristics Table 10-25. Electrical Parameters Symbol Parameter Input Levels V Low Level IL V High Level IH V Differential Input Sensivity DI Differential Input Common Mode V CM Range C Transceiver capacitance IN I ...
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... FS/HS Transceiver current consumption 1. Including 1 mA due to Pull-up/Pull-down current consumption. 41.2.1 USB High Speed Design Guidelines In order to facilitate hardware design, Atmel provides an application note on www.atmel.com. 32072C–AVR32–2010/03 Conditions If cable is connected, add 200µA (typical) due to Pull-up/Pull-down current consumption Conditions ...
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EBI Timings These timings are given for worst case process 85⋅C, VDDCORE = 1.65V, VDDIO = 3V and 40 pF load capacitance. 10.10.1 SMC Signals Table 10-30. SMC Clock Signal Symbol Parameter 1/(t ) SMC Controller Clock ...
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Table 10-32. SMC Read Signals with no Hold Settings Symbol Parameter SMC Data Setup before NRD High 19 SMC Data Hold after NRD High 20 SMC Data Setup before NCS High 21 SMC Data Hold after NCS High 22 Table ...
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Table 10-34. SMC Write Signals with No Hold Settings (NWE Controlled only) Symbol Parameter SMC Data Out Valid before NWE Rising 43 SMC Data Out Valid after NWE Rising 44 SMC NWE Pulse Width 45 Figure 10-5. SMC Signals for ...
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Figure 10-6. SMC Signals for NRD and NRW Controlled Accesses. A2-A25 A0/A1/NBS[3:0] NCS SMC9 NRD SMC19 D0 - D15 NWE 10.10.2 SDRAM Signals These timings are given for 10 pF load on SDCK and other signals. Table ...
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Table 10-36. SDRAM Clock Signal Symbol Parameter SDRAMC Bank Change before SDCK Rising Edge 13 SDRAMC Bank Change after SDCK Rising Edge 14 SDRAMC CAS Low before SDCK Rising Edge 15 SDRAMC CAS High after SDCK Rising Edge 16 SDRAMC ...
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Figure 10-7. SDRAMC Signals relative to SDCK. SDCK SDRAMC SDRAMC SDRAMC 1 2 SDCKE SDCS RAS CAS SDWE SDA10 A0 - A9, A11 - A13 BA0/BA1 DQM0 - DQM3 D0 - D15 Read D0 - D15 to Write 32072C–AVR32–2010/03 SDRAMC ...
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JTAG Characteristics 10.11.1 JTAG Interface Signals Table 10-37. JTAG Interface Timing Specification Symbol Parameter JTAG TCK Low Half-period 0 JTAG TCK High Half-period 1 JTAG TCK Period 2 JTAG TDI, TMS Setup before TCK High 3 JTAG TDI, TMS ...
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Figure 10-8. JTAG Interface Signals TCK TMS/TDI TDO Device Inputs Device Outputs 10.12 SPI Characteristics Figure 10-9. SPI Master mode with (CPOL= NCPHA (CPOL= NCPHA= 1) SPCK MISO MOSI 32072C–AVR32–2010/03 JTAG 2 JTAG 0 JTAG JTAG 3 JTAG ...
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Figure 10-10. SPI Master mode with (CPOL= 0 and NCPHA (CPOL= 1 and NCPHA= 0) SPCK MISO MOSI Figure 10-11. SPI Slave mode with (CPOL= 0 and NCPHA (CPOL= 1 and NCPHA= 0) SPCK MISO MOSI ...
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Table 10-38. SPI Timings Symbol Parameter MISO Setup time before SPCK rises SPI 0 (master) MISO Hold time after SPCK rises SPI 1 (master) SPCK rising to MOSI Delay SPI 2 (master) MISO Setup time before SPCK falls SPI 3 ...
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Flash Memory Characteristics The following table gives the device maximum operating frequency depending on the field FWS of the Flash FSR register. This field defines the number of wait states required to access the Flash Memory. Flash operating frequency ...
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Mechanical Characteristics 11.1 Thermal Considerations 11.1.1 Thermal Data Table 11-1 Table 11-1. Symbol θ JA θ JC θ JA θ JC θ JA θ JC 11.1.2 Junction Temperature The average chip-junction temperature where: • ...
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Package Drawings Figure 11-1. TFBGA 144 package drawing 32072C–AVR32–2010/03 AT32UC3A3/A4 74 ...
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Figure 11-2. LQFP-144 package drawing Table 11-2. Device and Package Maximum Weight 1300 Table 11-3. Package Characteristics Moisture Sensitivity Level Table 11-4. Package Reference JEDEC Drawing Reference JESD97 Classification 32072C–AVR32–2010/03 AT32UC3A3/A4 mg MSL3 MS-026 E3 75 ...
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Figure 11-3. VFBGA-100 package drawing 32072C–AVR32–2010/03 AT32UC3A3/A4 76 ...
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Soldering Profile Table 11-5 Table 11-5. Profile Feature Average Ramp-up Rate (217°C to Peak) Preheat Temperature 175°C ±25°C Time Maintained Above 217°C Time within 5°C of Actual Peak Temperature Peak Temperature Range Ramp-down Rate Time 25°C to Peak Temperature ...
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... Device Ordering Code AT32UC3A3256S AT32UC3A3256S-ALUT AT32UC3A3256S-ALUR AT32UC3A3256S-CTUT AT32UC3A3256S-CTUR AT32UC3A3256 AT32UC3A3256-ALUT AT32UC3A3256-ALUR AT32UC3A3256-CTUT AT32UC3A3256-CTUR AT32UC3A3128S AT32UC3A3128S-ALUT AT32UC3A3128S-ALUR AT32UC3A3128S-CTUT AT32UC3A3128S-CTUR AT32UC3A3128 AT32UC3A3128-ALUT AT32UC3A3128-ALUR AT32UC3A3128-CTUT AT32UC3A3128-CTUR AT32UC3A364S AT32UC3A364S-ALUT AT32UC3A364S-ALUR AT32UC3A364S-CTUT AT32UC3A364S-CTUR AT32UC3A364 AT32UC3A364-ALUT AT32UC3A364-ALUR AT32UC3A364-CTUT AT32UC3A364-CTUR AT32UC3A4256S AT32UC3A4256S-C1UT AT32UC3A4256S-C1UR AT32UC3A4256 AT32UC3A4256-C1UT AT32UC3A4256-C1UR AT32UC3A4128S AT32UC3A4128S-C1UT ...
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Errata 13.1 Rev. G 13.1.1 Processor and Architecture 1. LDM instruction with PC in the register list and without ++ increments Rp For LDM with PC in the register list: the instruction behaves as if the ++ field is ...
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USART 1. The NER register always returns zero. Fix/Workaround None 13.1.5 SPI 1. SPI Disable does not work in Slave mode Fix/workaround Read the last received data then perform a Software reset. 2. SPI Bad Serial Clock Generation on ...
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Fix/workaround: Disable and then enable the peripheral after the transfer error. 13.1.7 AES 1. URAD (Unspecified Register Access Detection Status) does not detect read accesses to the write-only KEYW[5..8]R registers Fix/Workaround None. 13.1.8 HMATRIX 1. In the HMATRIX PRAS and ...
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When the main clock is RCSYS, TIMER_CLOCK5 is equal to PBA clock When the main clock is generated from RCSYS, TIMER_CLOCK5 is equal to PBA Clock and not PBA Clock / 128. Fix/workaround None. 5. Clock sources will not ...
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Activate the sleep mode in the mode register and then perform an AD conversion. 13.2.5 SPI 1. SPI Bad Serial Clock Generation on 2nd chip_select when SCBR = 1, CPOL=1 and NCPHA=0 When multiple CS are in use, if one ...
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USART Control Register (CR). This will drive the RTS output high. After the next DMA trans- fer is started and a receive buffer is available, write a one to the RTSEN bit in the USART CR so that RTS will ...
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MCI 1. The busy signal of the responses R1b is not taken in account (excepting for CMD12 STOP_TRANSFER not possible to know the busy status of the card during the response (R1b) for the com- mands CMD7, ...
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All the multiply instructions do not work. Fix/Workaround Do not use the multiply instructions. 5. Hardware breakpoints on MAC instructions may corrupt the destination registerof the MAC instruction. Fix/Workaround Place breakpoints on earlier or later instructions. 13.3.3 MPU 1. Privilege ...
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USART - RTS output signal does not function properly in hardware handshaking mode The RTS signal is not generated properly when the USART receives data in hardware hand- shaking mode. When the Peripheral DMA receive buffer becomes full, the ...
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Datasheet Revision History Please note that the referring page numbers in this section are referred to this document. The referring revision in this section are referring to the document revision. 14.1 Rev. C – 03/10 1. 14.2 Rev. B ...
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Description ............................................................................................... 3 2 Blockdiagram ........................................................................................... 4 3 Signals Description ................................................................................. 6 4 Package and Pinout ............................................................................... 11 5 Power Considerations ........................................................................... 25 6 I/O Line Considerations ......................................................................... 26 7 Memories ................................................................................................ 27 8 Peripherals ............................................................................................. 32 9 Boot ...
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Mechanical Characteristics ................................................................... 73 12 Ordering Information ............................................................................. 78 13 Errata ....................................................................................................... 79 14 Datasheet Revision History .................................................................. 88 32072C–AVR32–2010/03 10.2 DC Characteristics ...........................................................................................47 10.3 Regulator characteristics .................................................................................49 10.4 Analog characteristics .....................................................................................49 10.5 Power Consumption ........................................................................................53 10.6 System Clock ...