ATSAM3S1CA-CU Atmel, ATSAM3S1CA-CU Datasheet - Page 51

IC MCU 32BIT 64KB FLASH 100BGA

ATSAM3S1CA-CU

Manufacturer Part Number
ATSAM3S1CA-CU
Description
IC MCU 32BIT 64KB FLASH 100BGA
Manufacturer
Atmel
Series
SAM3Sr
Datasheets

Specifications of ATSAM3S1CA-CU

Core Processor
ARM® Cortex-M3™
Core Size
32-Bit
Speed
64MHz
Connectivity
EBI/EMI, I²C, MMC, SPI, SSC, UART/USART, USB
Peripherals
Brown-out Detect/Reset, DMA, I²S, POR, PWM, WDT
Number Of I /o
79
Program Memory Size
64KB (64K x 8)
Program Memory Type
FLASH
Ram Size
16K x 8
Voltage - Supply (vcc/vdd)
1.62 V ~ 1.95 V
Data Converters
A/D 16x10/12b, D/A 2x12b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
100-LFBGA
Processor Series
ATSAM3x
Core
ARM Cortex M3
3rd Party Development Tools
JTRACE-CM3, MDK-ARM, RL-ARM, ULINK2
Development Tools By Supplier
ATSAM3S-EK
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Lead Free Status / Rohs Status
 Details

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
ATSAM3S1CA-CU
Manufacturer:
Atmel
Quantity:
10 000
Part Number:
ATSAM3S1CA-CUR
Manufacturer:
Atmel
Quantity:
10 000
12.11 Digital-to-Analog Converter (DAC)
12.12 Static Memory Controller
12.13 Analog Comparator
6500CS–ATARM–24-Jan-11
• Programmable gain: 1, 2, 4
• Up to 2 channel 12-bit DAC
• Up to 2 mega-samples conversion rate in single channel mode
• Flexible conversion range
• Multiple trigger sources for each channel
• 2 Sample/Hold (S/H) outputs
• Built-in offset and gain calibration
• Possibility to drive output to ground
• Possibility to use as input to analog comparator or ADC (as an internal wire and without S/H
• Two PDC channels
• Power reduction mode
• 16-Mbyte Address Space per Chip Select
• 8- bit Data Bus
• Word, Halfword, Byte Transfers
• Programmable Setup, Pulse And Hold Time for Read Signals per Chip Select
• Programmable Setup, Pulse And Hold Time for Write Signals per Chip Select
• Programmable Data Float Time per Chip Select
• External Wait Request
• Automatic Switch to Slow Clock Mode
• Asynchronous Read in Page Mode Supported: Page Size Ranges from 4 to 32 Bytes
• NAND FLASH additional logic supporting NAND Flash with Multiplexed Data/Address buses
• Hardware Configurable number of chip select from 1 to 4
• Programmable timing on a per chip select basis
• One analog comparator
• High speed option vs. low power option
• Selectable input hysteresis:
• Minus input selection:
• Plus input selection:
stage)
– 0, 20 mV, 50 mV
– DAC outputs
– Temperature Sensor
– ADVREF
– AD0 to AD3 ADC channels
– All analog inputs
SAM3S Summary
51

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