ATMEGA640-16AU Atmel, ATMEGA640-16AU Datasheet
ATMEGA640-16AU
Specifications of ATMEGA640-16AU
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ATMEGA640-16AU Summary of contents
Page 1
... Six/Twelve PWM Channels with Programmable Resolution from Bits (ATmega1281/2561, ATmega640/1280/2560) – Output Compare Modulator – 8/16-channel, 10-bit ADC (ATmega1281/2561, ATmega640/1280/2560) – Two/Four Programmable Serial USART (ATmega1281/2561, ATmega640/1280/2560) – Master/Slave SPI Serial Interface – Byte Oriented 2-wire Serial Interface – Programmable Watchdog Timer with Separate On-chip Oscillator – ...
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... Pin Configurations Figure 1-1. TQFP-pinout ATmega640/1280/2560 100 (OC0B) PG5 1 (RXD0/PCINT8) PE0 2 (TXD0) PE1 3 (XCK0/AIN0) PE2 4 (OC3A/AIN1) PE3 5 (OC3B/INT4) PE4 6 (OC3C/INT5) PE5 7 (T3/INT6) PE6 8 (CLKO/ICP3/INT7) PE7 9 VCC 10 GND 11 (RXD2) PH0 12 (TXD2) PH1 13 (XCK2) PH2 14 (OC4A) PH3 15 (OC4B) PH4 16 (OC4C) PH5 17 (OC2B) PH6 ...
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... Figure 1-2. CBGA-pinout ATmega640/1280/2560 Top view Table 1- Note: 2549MS–AVR–09/10 ATmega640/1280/1281/2560/2561 CBGA-pinout ATmega640/1280/2560 GND AREF PF0 PF2 AVCC PG5 PF1 PF3 PE2 PE0 PE1 PF4 PE3 PE4 PE5 PE6 PE7 PH0 PH1 PH3 VCC PH4 PH6 PB0 GND PB1 PB2 ...
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... PCINT5 ) PB5 16 (OC1B/ PCINT6 ) PB6 Note: 2549MS–AVR–09/10 ATmega640/1280/1281/2560/2561 INDEX CORNER ATmega1281/2561 The large center pad underneath the QFN/MLF package is made of metal and internally con- nected to GND. It should be soldered or glued to the board to ensure good mechanical stability. If the center pad is left unconnected, the package might loosen from the board. ...
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... Overview The ATmega640/1280/1281/2560/2561 is a low-power CMOS 8-bit microcontroller based on the AVR enhanced RISC architecture. By executing powerful instructions in a single clock cycle, the ATmega640/1280/1281/2560/2561 achieves throughputs approaching 1 MIPS per MHz allowing the system designer to optimize power consumption versus processing speed. 2.1 Block Diagram Figure 2-1 ...
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... RISC CPU with In-System Self-Programmable Flash on a monolithic chip, the Atmel ATmega640/1280/1281/2560/2561 is a powerful microcontroller that provides a highly flexible and cost effective solution to many embedded control applications. The ATmega640/1280/1281/2560/2561 AVR is supported with a full suite of program and sys debugger/simulators, in-circuit emulators, and evaluation kits. ...
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... Comparison Between ATmega1281/2561 and ATmega640/1280/2560 Each device in the ATmega640/1280/1281/2560/2561 family differs only in memory size and number of pins. Table 2-1. Configuration Summary Device Flash EEPROM ATmega640 64KB ATmega1280 128KB ATmega1281 128KB ATmega2560 256KB ATmega2561 256KB 2.3 Pin Descriptions 2.3.1 VCC Digital supply voltage. ...
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... The Port C pins are tri-stated when a reset condition becomes active, even if the clock is not running. Port C also serves the functions of special features of the ATmega640/1280/1281/2560/2561 as listed on 2.3.6 Port D (PD7..PD0) Port 8-bit bi-directional I/O port with internal pull-up resistors (selected for each bit). The Port D output buffers have symmetrical drive characteristics with both high sink and source capability ...
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... As inputs, Port L pins that are externally pulled low will source current if the pull-up resistors are activated. The Port L pins are tri-stated when a reset condition becomes active, even if the clock is not running. Port L also serves the functions of various special features of the ATmega640/1280/2560 as listed on 2.3.14 RESET Reset input ...
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... AVCC is the supply voltage pin for Port F and the A/D Converter. It should be externally con- nected to V through a low-pass filter. 2.3.18 AREF This is the analog reference pin for the A/D Converter. 2549MS–AVR–09/10 ATmega640/1280/1281/2560/2561 , even if the ADC is not used. If the ADC is used, it should be connected ...
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... I/O. Typically "LDS" and "STS" combined with "SBRS", "SBRC", "SBR", and "CBR". 5. Data Retention Reliability Qualification results show that the projected data retention failure rate is much less than 1 ppm over 20 years at 85°C or 100 years at 25°C. 2549MS–AVR–09/10 ATmega640/1280/1281/2560/2561 11 ...
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... DDRK DDK7 (0x106) PINK PINK7 (0x105) PORTJ PORTJ7 (0x104) DDRJ DDJ7 (0x103) PINJ PINJ7 (0x102) PORTH PORTH7 (0x101) DDRH DDH7 2549MS–AVR–09/10 ATmega640/1280/1281/2560/2561 Bit 6 Bit 5 Bit 4 Bit USART3 I/O Data Register - - - USART3 Baud Rate Register Low Byte - - - UMSEL30 UPM31 UPM30 ...
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... Reserved - (0xC6) UDR0 (0xC5) UBRR0H - (0xC4) UBRR0L (0xC3) Reserved - (0xC2) UCSR0C UMSEL01 (0xC1) UCSR0B RXCIE0 (0xC0) UCSR0A RXC0 (0xBF) Reserved - 2549MS–AVR–09/10 ATmega640/1280/1281/2560/2561 Bit 6 Bit 5 Bit 4 Bit 3 PINH6 PINH5 PINH4 PINH3 - - - - - - - - - - - - - - - - - ...
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... TCCR1C FOC1A (0x81) TCCR1B ICNC1 (0x80) TCCR1A COM1A1 (0x7F) DIDR1 - (0x7E) DIDR0 ADC7D (0x7D) DIDR2 ADC15D 2549MS–AVR–09/10 ATmega640/1280/1281/2560/2561 Bit 6 Bit 5 Bit 4 Bit TWAM5 TWAM4 TWAM3 TWAM2 TWEA TWSTA TWSTO TWWC 2-wire Serial Interface Data Register TWA5 TWA4 TWA3 ...
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... EEDR 0x1F (0x3F) EECR - 0x1E (0x3E) GPIOR0 0x1D (0x3D) EIMSK INT7 0x1C (0x3C) EIFR INTF7 0x1B (0x3B) PCIFR - 2549MS–AVR–09/10 ATmega640/1280/1281/2560/2561 Bit 6 Bit 5 Bit 4 Bit 3 REFS0 ADLAR MUX4 MUX3 ACME - - MUX5 ADSC ADATE ADIF ADIE ADC Data Register High byte ...
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... LD and ST instructions, $20 must be added to these addresses. The ATmega640/1280/1281/2560/2561 is a complex microcontroller with more peripheral units than can be supported within the 64 location reserved in Opcode for the IN and OUT instructions. For the Extended I/O space from $60 - $1FF in SRAM, only the ST/STS/STD and LD/LDS/LDD instructions can be used. 2549MS– ...
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... Branch if Half Carry Flag Set BRHC k Branch if Half Carry Flag Cleared BRTS k Branch if T Flag Set BRTC k Branch if T Flag Cleared 2549MS–AVR–09/10 ATmega640/1280/1281/2560/2561 Description Rd ← ← Rdh:Rdl ← Rdh:Rdl + K Rd ← ← ← ← Rdh:Rdl ← Rdh:Rdl - K Rd ← Rd • ← ...
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... LPM Rd, Z+ Load Program Memory and Post-Inc ELPM Extended Load Program Memory ELPM Rd, Z Extended Load Program Memory 2549MS–AVR–09/10 ATmega640/1280/1281/2560/2561 Description then PC ← then PC ← then PC ← then PC ← I/O(P,b) ← 1 I/O(P,b) ← 0 Rd(n+1) ← Rd(n), Rd(0) ← 0 Rd(n) ← Rd(n+1), Rd(7) ← 0 Rd(0)← ...
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... NOP No Operation SLEEP Sleep WDR Watchdog Reset BREAK Break Note: 2549MS–AVR–09/10 ATmega640/1280/1281/2560/2561 Description EICALL and EIJMP do not exist in ATmega640/1280/1281. ELPM does not exist in ATmega640. Operation Flags Rd ← (RAMPZ:Z), RAMPZ:Z ←RAMPZ:Z+1 None (Z) ← R1:R0 None Rd ← P None P ← Rr None STACK ← Rr None Rd ← ...
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... Thin (1.0 mm) Plastic Gull Wing Quad Flat Package (TQFP) 100C1 100-ball, Chip Ball Grid Array (CBGA) 2549MS–AVR–09/10 ATmega640/1280/1281/2560/2561 Ordering Code Package ATmega640V-8AU ATmega640V-8CU 100C1 ATmega640-16AU ATmega640-16CU 100C1 Package Type (1)(3) Operation Range 100A Industrial (-40°C to 85°C) 100A Industrial (-40°C to 85°C) ...
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... Body, Quad Flat No-lead/Micro Lead Frame Package (QFN/MLF) 100A 100-lead, Thin (1.0 mm) Plastic Gull Wing Quad Flat Package (TQFP) 100C1 100-ball, Chip Ball Grid Array (CBGA) 2549MS–AVR–09/10 ATmega640/1280/1281/2560/2561 Ordering Code ATmega1281V-8AU ATmega1281V-8MU ATmega1281-16AU ATmega1281-16MU 369. ...
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... Body, Quad Flat No-lead/Micro Lead Frame Package (QFN/MLF) 100A 100-lead, Thin (1.0 mm) Plastic Gull Wing Quad Flat Package (TQFP) 100C1 100-ball, Chip Ball Grid Array (CBGA) 2549MS–AVR–09/10 ATmega640/1280/1281/2560/2561 Ordering Code ATmega1280V-8AU ATmega1280V-8CU ATmega1280-16AU ATmega1280-16CU 369. ...
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... Body, Quad Flat No-lead/Micro Lead Frame Package (QFN/MLF) 100A 100-lead, Thin (1.0 mm) Plastic Gull Wing Quad Flat Package (TQFP) 100C1 100-ball, Chip Ball Grid Array (CBGA) 2549MS–AVR–09/10 ATmega640/1280/1281/2560/2561 Ordering Code ATmega2561V-8AU ATmega2561V-8MU ATmega2561-16AU ATmega2561-16MU 369. ...
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... Body, Quad Flat No-lead/Micro Lead Frame Package (QFN/MLF) 100A 100-lead, Thin (1.0 mm) Plastic Gull Wing Quad Flat Package (TQFP) 100C1 100-ball, Chip Ball Grid Array (CBGA) 2549MS–AVR–09/10 ATmega640/1280/1281/2560/2561 Ordering Code ATmega2560V-8AU ATmega2560V-8CU ATmega2560-16AU ATmega2560-16CU 369. ...
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... This package conforms to JEDEC reference MS-026, Variation AED. 2. Dimensions D1 and E1 do not include mold protrusion. Allowable protrusion is 0.25 mm per side. Dimensions D1 and E1 are maximum plastic body size dimensions including mold mismatch. 3. Lead coplanarity is 0.08 mm maximum. 2325 Orchard Parkway San Jose, CA 95131 R 2549MS–AVR–09/10 ATmega640/1280/1281/2560/2561 B PIN 1 IDENTIFIER TITLE 100A, 100-lead Body Size, 1 ...
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... D e 0.90 TYP 0.90 TYP 2325 Orchard Parkway San Jose, CA 95131 R 2549MS–AVR–09/10 ATmega640/1280/1281/2560/2561 E Marked A1 Identifier TOP VIEW Øb A1 Corner BOTTOM VIEW TITLE 100C1, 100-ball 1.2 mm Body, Ball Pitch 0.80 mm Chip Array BGA Package (CBGA) 0.12 Z SIDE VIEW A ...
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... JEDEC reference MS-026, Variation AEB. 2. Dimensions D1 and E1 do not include mold protrusion. Allowable protrusion is 0.25 mm per side. Dimensions D1 and E1 are maximum plastic body size dimensions including mold mismatch. 3. Lead coplanarity is 0.10 mm maximum. 2325 Orchard Parkway San Jose, CA 95131 R 2549MS–AVR–09/10 ATmega640/1280/1281/2560/2561 B PIN 1 IDENTIFIER TITLE 64A, 64-lead Body Size, 1 ...
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... Marked Pin TOP VIEW BOTTOM VIEW Note: 1. JEDEC Standard MO-220, (SAW Singulation) Fig. 1, VMMD. 2. Dimension and tolerance conform to ASMEY14.5M-1994. 2325 Orchard Parkway San Jose, CA 95131 R 2549MS–AVR–09/10 ATmega640/1280/1281/2560/2561 D E Pin #1 Corner Pin #1 1 Option A Triangle 2 3 Option B Pin #1 Chamfer (C 0.30) Option C ...
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... Errata 10.1 ATmega640 rev. A • Inaccurate ADC conversion in differential mode with 200× gain. • High current consumption in sleep mode. 1. Inaccurate ADC conversion in differential mode with 200× gain With AVCC <3.6V, random conversions will be inaccurate. Typical absolute accuracy may reach 64 LSB. ...
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... This is done by writing the CLKPR register before entering the boot section of the code. 2. Part does not work under 2.4 volts The part does not execute code correctly below 2.4 volts. 2549MS–AVR–09/10 ATmega640/1280/1281/2560/2561 30 ...
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... When the Memory Lock Bits LB2 and LB1 are programmed to mode 3, EEPROM read does not work from the application code. Problem Fix/Workaround Do not set Lock Bit Protection Mode 3 when the application code needs to read from EEPROM. 10.9 ATmega2561 rev known errata. 10.10 ATmega2561 rev. D Not sampled. 2549MS–AVR–09/10 ATmega640/1280/1281/2560/2561 31 ...
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... The ADC has high noise in differential mode. It can give LSB error. Problem Fix/Workaround Use only the 7 MSB of the result when using the ADC in differential mode. 4. Internal ADC reference has too low value The internal ADC reference has a value lower than specified. Problem Fix/Workaround - Use AVCC or external reference. 2549MS–AVR–09/10 ATmega640/1280/1281/2560/2561 32 ...
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... EEPROM read from application code does not work in Lock Bit Mode 3 When the Memory Lock Bits LB2 and LB1 are programmed to mode 3, EEPROM read does not work from the application code. Problem Fix/Workaround Do not set Lock Bit Protection Mode 3 when the application code needs to read from EEPROM. 2549MS–AVR–09/10 ATmega640/1280/1281/2560/2561 33 ...
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... Added “System and Reset Characteristics” on page Updated “SPI Timing Characteristics” on page Updated “ADC Characteristics – Preliminary Data” on page Updated ordering code in “ATmega640” on page and in Figure 25-10 on page 3. Table 30-7 on page 376 have been changed has been changed. ...
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... Rev. 2549I-07/ 11.6 Rev. 2549H-06/ 2549MS–AVR–09/10 ATmega640/1280/1281/2560/2561 Updated Table 1-1 on page 3. Updated “Pin Descriptions” on page Updated “Stack Pointer” on page Updated “Bit 1 – EEPE: EEPROM Programming Enable” on page Updated Assembly code example in after setting the ACBG bit or enabling the ADC, the user must always allow the reference to start up before the output from the Analog Compar- ator or ADC is used ...
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... Rev. 2549D-12/ 2549MS–AVR–09/10 ATmega640/1280/1281/2560/2561 Updated “Features” on page 1. Added Figure 1-2 on page 3, Table 1-1 on page Updated “” on page 46. Updated “Power Management and Sleep Modes” on page Updated note for Table 11-1 on page Updated Figure 25-9 on page 285 Updated “ ...
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... V Updated “Ordering Information” on page Updated “Packaging Information” on page 64M2. Updated “Errata” on page 29. JTAG ID/Signature for ATmega640 updated: 0x9608. Updated Table 12-7 on page 81. Updated “Serial Programming Instruction set” on page Updated “Errata” on page 29. Initial version. ...
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... Disclaimer: The information in this document is provided in connection with Atmel products. No license, express or implied, by estoppel or otherwise, to any intellectual property right is granted by this document or in connection with the sale of Atmel products. EXCEPT AS SET FORTH IN ATMEL’S TERMS AND CONDI- TIONS OF SALE LOCATED ON ATMEL’S WEB SITE, ATMEL ASSUMES NO LIABILITY WHATSOEVER AND DISCLAIMS ANY EXPRESS, IMPLIED OR STATUTORY WARRANTY RELATING TO ITS PRODUCTS INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTY OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, OR NON-INFRINGEMENT ...