DSPIC30F6012T-20E/PF Microchip Technology, DSPIC30F6012T-20E/PF Datasheet - Page 10

• Manufacturer Part Number: DSPIC30F6012T-20E/PF
• Description: IC DSPIC MCU/DSP 144K 64TQFP
• Manufacturer: Microchip Technology
• Series: dsPIC™ 30Fr

Specifications of DSPIC30F6012T-20E/PF

• Core Processor: dsPIC
• Core Size: 16-Bit
• Speed: 20 MIPS
• Connectivity: CAN, I²C, SPI, UART/USART
• Peripherals: AC'97, Brown-out Detect/Reset, I²S, LVD, POR, PWM, WDT
• Number Of I /o: 52
• Program Memory Size: 144KB (48K x 24)
• Program Memory Type: FLASH
• Eeprom Size: 4K x 8
• Ram Size: 8K x 8
• Voltage - Supply (vcc/vdd): 2.5 V ~ 5.5 V
• Data Converters: A/D 16x12b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 125°C
• Package / Case: 64-TQFP, 64-VQFP
• For Use With: XLT64PT4 - SOCKET TRAN ICE 64MQFP/TQFPAC164313 - MODULE SKT FOR PM3 64PFAC30F002 - MODULE SOCKET DSPIC30F 64TQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: DSPIC30F6012T20EP

dsPIC30F6011/6012/6013/6014
10. Module: CPU
EXAMPLE 9:
DS80456D-page 10
__T1Interrupt:
When interrupt nesting is enabled (or NSTDIS bit
(INTCON1<15>) is ‘0’), the following sequence of
events will lead to an address error trap:
1. REPEAT loop is active.
2. An interrupt is generated during the execution
3. The CPU executes the Interrupt Service
4. Within the ISR, when the CPU is executing the
Work around
Processing of Interrupt Service Routines should
be disabled while the RETFIE instruction is being
executed. This may be accomplished in two
different ways:
1. Place a DISI instruction immediately before
2. Immediately prior to executing the RETFIE
PUSH
.......
BCLR
POP
DISI
RETFIE
of the REPEAT loop.
Routine (ISR) of the source causing the
interrupt.
first instruction cycle of the 3-cycle RETFIE
(Return-from-Interrupt) instruction, a second
interrupt is generated by a source with a higher
interrupt priority.
the RETFIE instruction in all Interrupt Service
Routines of interrupt sources that may be
interrupted by other higher priority interrupt
sources (with priority levels 1 through 6). This
is shown in Example 9 in the Timer1 ISR. In
this example, a DISI instruction inhibits level 1
through level 6 interrupts for 2 instruction
cycles, while the RETFIE instruction is
executed.
instruction, increase the CPU priority level by
modifying the IPL<2:0> bits (SR<7:5>) to ‘111’
as shown in Example 10. This will disable all
interrupts between priority levels 1 through 7.
W0
IFS0, #T1IF
W0
#1
;Another interrupt occurs
;here and it is processed
;correctly
DISI BEFORE RETFIE
;Timer1 ISR
;This line optional
;This line optional
EXAMPLE 10:
11. Module: CPU
__T1Interrupt:
Affected Silicon Revisions
When a user executes a DISI #7, for example,
this will disable interrupts for 7 + 1 cycles (7 + the
DISI instruction itself). In this case, the DISI
instruction uses a counter which counts down from
7 to 0. The counter is loaded with 7 at the end of
the DISI instruction.
If the user code executes another DISI on the
instruction cycle where the DISI counter has
become zero, the new DISI count is loaded, but the
DISI state machine does not properly re-engage
and continue to disable interrupts. At this point, all
interrupts are enabled. The next time the user code
executes a DISI instruction, the feature will act
normally and block interrupts.
In summary, it is only when a DISI execution is
coincident with the current DISI count = 0, that the
issue occurs. Executing a DISI instruction before
the DISI counter reaches zero will not produce
this error. In this case, the DISI counter is loaded
with the new value, and interrupts remain disabled
until the counter becomes zero.
Work around
When executing multiple DISI instructions within
the source code, make sure that subsequent DISI
instructions have at least one instruction cycle
between the time that the DISI counter
decrements to zero and the next DISI instruction.
Alternatively, make sure that subsequent DISI
instructions are called before the DISI counter
decrements to zero.
Affected Silicon Revisions
PUSH
.......
BCLR
MOV.B
MOV.B
POP
RETFIE
A3
A3
X
X
B1
B1
X
X
W0
IFS0, #T1IF
#0xE0, W0
WREG, SR
W0
B2
B2
;Another interrupt occurs
;here and it is processed
;correctly
X
X
RAISE IPL BEFORE RETFIE
;Timer1 ISR
© 2010 Microchip Technology Inc.