EP7312-CR Cirrus Logic Inc, EP7312-CR Datasheet - Page 24

IC ARM720T MCU 74MHZ 204-TFBGA

EP7312-CR

Manufacturer Part Number
EP7312-CR
Description
IC ARM720T MCU 74MHZ 204-TFBGA
Manufacturer
Cirrus Logic Inc
Series
EP7r
Datasheet

Specifications of EP7312-CR

Core Processor
ARM7
Core Size
32-Bit
Speed
74MHz
Connectivity
Codec, DAI, EBI/EMI, IrDA, Keypad, SPI/Microwire1, UART/USART
Peripherals
LCD, LED, MaverickKey, PWM
Number Of I /o
27
Program Memory Type
ROMless
Ram Size
56K x 8
Voltage - Supply (vcc/vdd)
2.3 V ~ 2.7 V
Oscillator Type
External
Operating Temperature
0°C ~ 70°C
Package / Case
204-TFBGA
Processor Series
EP73xx
Core
ARM720T
Data Bus Width
32 bit
3rd Party Development Tools
MDK-ARM, RL-ARM, ULINK2
Development Tools By Supplier
EDB7312
For Use With
598-1209 - KIT DEVELOPMENT EP73XX ARM7
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Eeprom Size
-
Program Memory Size
-
Data Converters
-
Lead Free Status / Rohs Status
No
Other names
598-1235

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EP7312
High-Performance, Low-Power System on Chip
Static Memory Burst Read Cycle
24
EXPRDY
EXPCLK
WRITE
WORD
WORD
nMWE
nMOE
HALF
nCS
A
D
Note: 1. Four cycles are shown in the above diagram (minimum wait states, 1-0-0-0). This is the maximum number of consecutive
cycles that can be driven. The number of consecutive cycles can be programmed from 2 to 4, inclusively.
2. The cycle time can be extended by integer multiples of the clock period (22 ns at 45 MHz, 27 ns at 36 MHz, 54 ns at
18.432 MHz, and 77 ns at 13 MHz), by either driving EXPRDY low and/or by programming a number of wait states. EXPRDY is
sampled on the falling edge of EXPCLK before the data transfer. If low at this point, the transfer is delayed by one clock period
where EXPRDY is sampled again. EXPCLK need not be referenced when driving EXPRDY, but is shown for clarity.
3. Consecutive reads with sequential access enabled are identical except that the sequential access wait state field is used to
determine the number of wait states, and no idle cycles are inserted between successive non-sequential ROM/expansion
cycles. This improves performance so the SQAEN bit should always be set where possible.
4. Address, Halfword, Word, and Write hold state until next cycle.
t
CSd
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Ad
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WRd
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MOEd
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HWd
WDd
t
Figure 9. Static Memory Burst Read Cycle Timing Measurement
EXs
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Copyright Cirrus Logic, Inc. 2005
(All Rights Reserved)
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