W77E058A40PL Nuvoton Technology Corporation of America, W77E058A40PL Datasheet
W77E058A40PL
Specifications of W77E058A40PL
Available stocks
Related parts for W77E058A40PL
W77E058A40PL Summary of contents
Page 1
Table of Contents- 1. GENERAL DESCRIPTION ......................................................................................................... 3 2. FEATURES ................................................................................................................................. 3 3. PIN CONFIGURATIONS ............................................................................................................ 4 4. PIN DESCRIPTION..................................................................................................................... 5 5. BLOCK DIAGRAM ...................................................................................................................... 7 6. FUNCTIONAL DESCRIPTION ................................................................................................... 8 7. MEMORY ORGANIZATION ..................................................................................................... 10 7.1 Program Memory .......................................................................................................... ...
Page 2
WACHDOG TIMER................................................................................................................... 57 14.1 Watchdog Control ......................................................................................................... 59 14.2 Clock Control ................................................................................................................ 59 15. SERIAL PORT .......................................................................................................................... 59 15.1 Mode 0 .......................................................................................................................... 60 15.2 Mode 1 .......................................................................................................................... 61 15.3 Mode 2 .......................................................................................................................... 62 15.4 Mode 3 .......................................................................................................................... 64 15.5 ...
Page 3
... Dual 16-bit Data Pointers • Software programmable access cycle to external RAM/peripherals • Packages: − DIP 40: W77E58-40 − PLCC 44: W77E58P-40, − QFP 44: W77E58F-40, − Lead Free DIP 40: W77E058A40DL − Lead Free PLCC 44: W77E058A40PL − Lead Free PQFP 44: W77E058A40FL Publication Release Date: February 17, 2005 - 3 - W77E58 Revision A6 ...
Page 4
PIN CONFIGURATIONS 40-Pin DIP (W77E58) 44-Pin PLCC (W77E58P ...
Page 5
PIN DESCRIPTION SYMBOL TYPE EXTERNAL ACCESS ENABLE: This pin forces the processor to execute out of external ROM. It should be kept high to access internal ROM. The ROM I EA address and data will not be present on ...
Page 6
Pin Description, continued SYMBOL TYPE PORT 3: Port bi-directional I/O port with internal pull-ups. All bits have alternate functions, which are described below: RXD(P3.0) : Serial Port 0 input TXD(P3.1) : Serial Port 0 output INT0 (P3.2) ...
Page 7
BLOCK DIAGRAM P1.0 Port Port 1 1 P1.7 Latch Interrupt Timer 2 Timer 0 Timer 1 2 UARTs Port 3 Port P3.0 Latch 3 P3.7 Port 4 Latch P4.0 Port 4 Oscillator P4.3 XTAL1 XTAL2 ACC B T1 Register ...
Page 8
FUNCTIONAL DESCRIPTION The W77E58 is 8052 pin compatible and instruction set compatible. It includes the resources of the standard 8052 such as four 8-bit I/O Ports, three 16-bit timer/counters, full duplex serial port and interrupt sources. The W77E58 features ...
Page 9
Timers The W77E58 has three 16-bit timers that are functionally similar to the timers of the 8052 family. When used as timers, they can be set to run at either 4 clocks or 12 clocks per count, thus providing the ...
Page 10
MEMORY ORGANIZATION The W77E58 separates the memory into two separate sections, the Program Memory and the Data Memory. The Program Memory is used to store the instruction op-codes, while the Data Memory is used to store data or for ...
Page 11
FFh Indirect RAM 80h 7Fh Direct RAM 30h 2Fh 2Eh 2Dh 2Ch 2Bh 2Ah 29h 4F ...
Page 12
SPECIAL FUNCTION REGISTERS The W77E58 uses Special Function Registers (SFRs) to control and monitor peripherals and their Modes. The SFRs reside in the register locations 80-FFh and are accessed by direct addressing only. Some of the SFRs are bit ...
Page 13
A brief description of the SFRs now follows. Port 0 Bit: 7 P0.7 Mnemonic: P0 Port open-drain bi-directional I/O port. This port also provides a multiplexed low order address/data bus during accesses to external memory. Stack Pointer ...
Page 14
This is the low byte of the new additional 16-bit data pointer that has been added to the W77E58. The user can switch between DPL, DPH and DPL1, DPH1 simply by setting register DPS = 1. The instructions that use ...
Page 15
Timer Control Bit: 7 TF1 Mnemonic: TCON TF1: Timer 1 overflow flag: This bit is set when Timer 1 overflows cleared automatically when the program does a timer 1 interrupt service routine. Software can also set or clear ...
Page 16
M1, M0: Mode Select bits Mode 0 0 Mode 0: 8-bits with 5-bit prescale Mode 1: 18-bits, no prescale Mode 2: 8-bits with auto-reload from THx 1 1 Mode 3: (Timer 0) TL0 is ...
Page 17
Clock Control Bit: 7 WD1 Mnemonic: CKCON WD1-0: Watchdog timer mode select bits: These bits determine the time-out period for the watchdog timer. In all four time-out options the reset time-out is 512 clocks more than the interrupt time- out ...
Page 18
Port 1 Bit: 7 P1.7 Mnemonic: P1 P1.7-0: General purpose I/O port. Most instructions will read the port pins in case of a port read access, however in case of read-modify-write instructions, the port latch is read. Some pins also ...
Page 19
Serial Port Control Bit: 7 SM0/FE Mnemonic: SCON SM0/FE: Serial port 0, Mode 0 bit or Framing Error Flag: The SMOD0 bit in PCON SFR determines whether this bit acts as SM0 or as FE. The operation of SM0 is ...
Page 20
Poot 2 Bit: 7 P2.7 Mnemonic: P2 P2.7-0: Port bi-directional I/O port with internal pull-ups. This port also provides the upper address bits for accesses to external memory. Port 4 Bit Mnemonic: P4 P4.3-0: Port ...
Page 21
Slave Address 1 Bit: 7 Mnemonic: SADDR1 SADDR1: The SADDR1 should be programmed to the given or broadcast address for serial port 1 to which the slave processor is designated. Port 3 Bit: 7 P3.7 Mnemonic: P3 P3.7-0: General purpose ...
Page 22
Slave Address Mask Enable Bit: 7 Mnemonic: SADEN SADEN: This register enables the Automatic Address Recognition feature of the Serial port 0. When a bit in the SADEN is set to 1, the same bit location in SADDR will be ...
Page 23
This results in faster synchronous serial communication. REN_1: Receive enable: When set to 1 serial reception is enabled, otherwise reception is disabled. TB8_1: This is the 9th bit to be transmitted in ...
Page 24
Power Management Register Bit: 7 CD1 Mnemonic: PMR CD1, CD0: Clock Divide Control. These bit selects the number of clocks required to generate one machine cycle. There are three modes including divide 1024. Switching between modes ...
Page 25
XTUP:Crystal Oscillator Warm-up Status. when set, this bit indicates CPU has detected clock to be ready. Each time the crystal oscillator is restarted by exit from power down mode or the XTOFF bit is set, hardware will clear this bit. ...
Page 26
TCLK: Transmit Clock Flag: This bit determines the serial port 0 time-base when transmitting data in modes 1 and set to 0, the timer 1 overflow is used to generate the baud rate clock otherwise timer ...
Page 27
Timer 2 Capture LSB Bit: 7 RCAP2L.7 RCAP2L.6 Mnemonic: RCAP2L RCAP2L:This register is used to capture the TL2 value when a timer 2 is configured in capture mode. RCAP2L is also used as the LSB of a 16-bit reload value ...
Page 28
RS.1-0: Register bank select bits: RS1 RS0 OV: Overflow flag: Set when a carry was generated from the seventh bit but not from the 8th bit as a result of the previous ...
Page 29
Extended Interrupt Enable Bit Mnemonic: EIE EIE.7-5:Reserved bits, will read high EWDI: Enable Watchdog timer interrupt EX5: External Interrupt 5 Enable. EX4: External Interrupt 4 Enable. EX3: External Interrupt 3 Enable. EX2: External Interrupt 2 Enable. B Register ...
Page 30
INSTRUCTION The W77E58 executes all the instructions of the standard 8032 family. The operation of these instructions, their effect on the flag bits and the status bits is exactly the same. However, timing of these instructions is different. The ...
Page 31
Table 3. Instruction Timing for W77E58, continued HEX Instruction Op-Code ADDC ADDC ADDC ADDC ADDC ADDC ADDC ADDC A, ...
Page 32
Table 3. Instruction Timing for W77E58, continued HEX Instruction Op-Code CLR A E4 CPL A F4 CLR C C3 CLR bit C2 CPL C B3 CPL bit B2 DEC A 14 DEC R0 18 DEC R1 19 DEC R2 1A ...
Page 33
Table 3. Instruction Timing for W77E58, continued HEX Instruction Op-Code INC R6 0E INC R7 0F INC @R0 06 INC @R1 07 INC direct 05 INC DPTR A3 JMP @A+DPTR 73 JZ rel 60 JNZ rel 70 JC rel 40 ...
Page 34
Table 3. Instruction Timing for W77E58, continued HEX Instruction Op-Code MOV R1, direct A9 MOV R2, direct AA MOV R3, direct AB MOV R4, direct AC MOV R5, direct AD MOV R6, direct AE MOV R7, direct AF MOV R0, ...
Page 35
Table 3. Instruction Timing for W77E58, continued HEX Instruction Op-Code MOVX A, @R0 E2 MOVX A, @R1 E3 MOVX A, @DPTR E0 MOVX @R0 MOVX @R1 MOVX @DPTR MOV C, bit A2 MOV bit, ...
Page 36
Table 3. Instruction Timing for W77E58, continued HEX Instruction Op-Code SUBB SUBB SUBB SUBB SUBB SUBB SUBB A, @R0 96 SUBB A, ...
Page 37
Instruction Timing The instruction timing for the W77E58 is an important aspect, especially for those users who wish to use software instructions to generate timing delays. Also, it provides the user with an insight into the timing differences between ...
Page 38
Instruction Fetch C1 C2 CLK ALE PSEN PC AD7-0 PORT 2 Instruction Fetch CLK ALE PSEN A7-0 OP-CODE AD7-0 PORT 2 Address A15-8 Figure 5. Three Cycle Instruction Timing Operand Fetch OP-CODE PC+1 ...
Page 39
Instruction Fetch CLK ALE PSEN AD7-0 A7-0 OP-CODE Port 2 Address A15-8 Instruction Fetch Operand Fetch CLK ALE PSEN A7-0 OP-CODE AD7-0 Address A15-8 PORT 2 Operand Fetch Operand Fetch C1 ...
Page 40
MOVX Instruction The W77E58, like the standard 8032, uses the MOVX instruction to access external Data Memory. This Data Memory includes both off-chip memory as well as memory mapped peripherals. While the results of the MOVX instruction are the ...
Page 41
Machine cycles in standard 8032 = 10 + (26 * CNT) Machine cycles in W77E58 = 10 + (26 * CNT) If CNT = 50 Clock cycles in standard 8032= ((10 + (26 *50 (10 + 1300) ...
Page 42
MOVX instructions that last from machine cycles in length. Note that the stretching of the instruction only results in the elongation of the MOVX instruction the state of the ...
Page 43
Last Cycle of Previous Instruction CLK ALE PSEN WR D0-D7 A0-A7 PORT 0 MOVX Inst. Address MOVX Inst. PORT 2 A15-A8 Figure 9. Data Memory Write with Stretch Value = 1 Last Cycle First Machine Cycle ...
Page 44
Wait State Control Signal Either with the software using stretch value to change the required machine cycle of MOVX instruction, the W77E58 provides another hardware signal WAIT to implement the wider duration of external data access timing. This wait ...
Page 45
So the Economy mode may provide a lower power consumption than idle mode. Software invokes the Economy mode by setting the appropriate bits in the SFRs. Setting the bits ...
Page 46
The W77E58 will exit the Power Down mode with a reset external interrupt pin enabled as level detect. An external reset can be used to exit the Power down state. The high on RST pin terminates the ...
Page 47
Watchdog Timer Reset The Watchdog timer is a free running timer with programmable time-out intervals. The user can clear the watchdog timer at any time, causing it to restart the count. When the time-out interval is reached an interrupt ...
Page 48
Table 6. SFR Reset Value, continued SFR Name SCON SBUF P2 SADDR1 SCON1 ROMMAP EXIF P4 The WDCON SFR bits are set/cleared in reset condition depending on the source of the reset. External reset WDCON 0x0x0xx0b The POR bit WDCON.6 ...
Page 49
The Timer 0 and 1 Interrupts are generated by the TF0 and TF1 flags. These flags are set by the overflow in the Timer 0 and Timer 1. The TF0 and TF1 flags are automatically cleared by the hardware when ...
Page 50
The interrupt flags are sampled every machine cycle. In the same machine cycle, the sampled interrupts are polled and their priority is resolved. If certain conditions are met then the hardware will execute an internally generated LCALL instruction which will ...
Page 51
Interrupt Response Time The response time for each interrupt source depends on several factors, such as the nature of the interrupt and the instruction underway. In the case of external interrupts INT0 to INT5 , they are sampled at ...
Page 52
Timer/Counter 0 and bit 6 of TMOD selects the function for Timer/Counter 1. In addition each Timer/Counter can be set to operate in any one of four possible modes. The mode selection is done by bits M0 and M1 in ...
Page 53
Mode 1 Mode 1 is similar to Mode 0 except that the counting register forms a 16 bit counter, rather than a 13 bit counter. This means that all the bits of THx and TLx are used. Roll-over occurs ...
Page 54
Timer/Counter 2 Timer/Counter bit up/down counter which is configured by the T2MOD register and controlled by the T2CON register. Timer/Counter 2 is equipped with a capture/reload capability. As with the Timer 0 and Timer 1 ...
Page 55
Clock Source 1/4 Mode input div osc/1 div osc/16 div. by 1024 osc/256 1/ P1.0 TR2 = T2CON.2 T2EX = P1.1 EXEN2 = T2CON.3 13.3.2 Auto-Reload Mode, Counting up The auto-reload mode as an ...
Page 56
T2EX pin this pin cause the counter to count up. An overflow while counting up will cause the counter to be reloaded with the contents of the capture registers. The next ...
Page 57
Programmable Clock-out Timer 2 is equipped with a new clock-out feature which outputs a 50% duty cycle clock on P1.0. It can be invoked as a programmable clock generator. To configure Timer 2 with clock-out mode, software must initiate ...
Page 58
Clock Source Mode input div osc/1 div osc/16 17 div. by 1024 osc/256 20 Reset Watchdog 23 RWT (WDCON.0) The Watchdog timer should first be restarted by using RWT. This ensures that the timer starts ...
Page 59
Table 9. Time-out values for the watchdog timer Watchdog WD1 WD0 Interval The Watchdog timer will de disabled by a power-on/fail reset. The Watchdog ...
Page 60
In the asynchronous mode, full duplex operation is available. This means that it can simultaneously transmit and receive data. The transmit register and the receive buffer are both addressed as ...
Page 61
The TI flag is set high in C1 following the end of transmission of the last bit. The serial port will receive data when REN is 1 and RI is zero. The shift clock (TxD) will be activated and the ...
Page 62
Timer 1 Timer 2 Overflow Overflow (for Serial Port 0 only) 2 SMOD (SMOD_1) TCLK RCLK SAMPLE 1-TO-0 DETECTOR RXD 15.3 Mode 2 This mode uses a total of 11 bits in ...
Page 63
Clock Source Mode input div osc/2 div osc/32 div. by 1024 osc/512 Write to 2 SMOD (SMOD_1 SAMPLE 1-TO-0 DETECTOR RXD If the first bit detected after the falling edge of RxD ...
Page 64
Mode 3 This mode is similar to Mode 2 in all respects, except that the baud rate is programmable. The user must first initialize the Serial related SFR SCON before any communication can take place. This involves selection of ...
Page 65
Framing Error Detection A Frame Error occurs when a valid stop bit is not detected. This could indicate incorrect serial data communication. Typically the frame error is due to noise and contention on the serial communication line. The W77E58 ...
Page 66
The following example shows how the user can define the Given Address to address different slaves. Slave 1: SADDR 1010 0100 SADEN 1111 1010 Given 1010 0x0x Slave 2: SADDR 1010 0111 SADEN 1111 1001 Given 1010 0xx1 The Given ...
Page 67
When the software writes AAh to the TA SFR, a counter is started. This counter waits for 3 machine cycles looking for a write of 55h to TA. If the second write (55h) occurs within 3 machine cycles of the ...
Page 68
ON-CHIP FLASH EPROM CHARACTERISTICS The W77E58 has several modes to program the on-chip Flash EPROM. All these operations are configured by the pins RST, ALE, PSEN , A9CTRL(P3.0), A13CTRL(P3.1), A14CTRL(P3.2), OECTRL(P3.3), CE (P3.6), OE (P3.7), A0(P1.0) and V P1.7−P1.0) ...
Page 69
Operations P3.0 P3.1 (A9 (A13 CTRL) CTRL) Read 0 0 Output Disable 0 0 Program 0 0 Program Verify 0 0 Erase 1 0 Erase Verify 1 0 Program/Erase X 0 Inhibit Notes: 1. All these operations happen in RST ...
Page 70
Security Bits During the on-chip Flash EPROM operation mode, the Flash EPROM can be programmed and verified repeatedly. Until the code inside the Flash EPROM is confirmed OK, the code can be protected. The protection of Flash EPROM and those ...
Page 71
B0: Lock bit This bit is used to protect the customer's program code in the W77E58. It may be set after the programmer finishes the programming and verifies sequence. Once this bit is set to logic 0, both the Flash ...
Page 72
D.C. Characteristics − ± ° C, Fosc = 20 MHz, unless otherwise specified PARAMETER Operating Voltage Operating Current Idle Current Power Down Current Input Current P1, P2, ...
Page 73
A.C. Characteristics Note: Duty cycle is 50%. External Clock Characteristics PARAMETER SYMBOL Clock High Time t CHCX Clock Low Time t CLCX Clock Rise Time t CLCH Clock Fall Time t CHCL AC Specification PARAMETER Oscillator Frequency ALE Pulse ...
Page 74
AC Specification, continued PARAMETER Input Instruction Hold After PSEN Input Instruction Float After PSEN Port 0 Address to Valid Instr. In Port 2 Address to Valid Instr. In PSEN Low to Address Float Data Hold After Read Data Float After ...
Page 75
Movx Characteristics Using Strech Memory Cycles, continued PARAMETER RD WR ALE Low to or Low RD WR Port 0 Address to or Low RD WR Port 2 Address to or Low Data Valid to WR Transition Data Hold after Write ...
Page 76
Explanation of Logic Symbols In order to maintain compatibility with the original 8051 family, this device specifies the same parameter for each device, using the same symbols. The explanation of the symbols is as follows. t Time C Clock H ...
Page 77
Data Memory Read Cycle ALE PSEN RD PORT 0 INSTRUCTION IN PORT 2 Data Memory Write Cycle ALE PSEN WR PORT 0 INSTRUCTION IN PORT 2 t LLDV t LLWL t RLRH t LLAX1 t RLDV t AVLL t t ...
Page 78
TYPICAL APPLICATION CIRCUITS 19.1 Expanded External Program Memory and Crystal XTAL1 XTAL2 CRYSTAL 8 RST INT1 P1.0 2 ...
Page 79
Typical Application Circuits, continued 19.2 Expanded External Data Memory and Oscillator OSCILLATOR 8 20. PACKAGE DIMENSIONS 20.1 ...
Page 80
Package Dimensions, continued 20.2 44-pin PLCC θ Seating Plane 20.3 44-pin QFP See ...
Page 81
VERSION HISTORY VERSION DATE A1 Aug. 2001 A2 Sep. 2001 A3 Mar. 2002 A4 May. 2004 A5 June, 2004 A6 Feb. 17, 2005 Headquarters No. 4, Creation Rd. III, Science-Based Industrial Park, Hsinchu, Taiwan TEL: 886-3-5770066 FAX: 886-3-5665577 http://www.winbond.com.tw/ ...