W77E058A40PL Nuvoton Technology Corporation of America, W77E058A40PL Datasheet - Page 22

• Manufacturer Part Number: W77E058A40PL
• Description: IC MCU 8-BIT 32K FLASH 44-PLCC
• Manufacturer: Nuvoton Technology Corporation of America
• Series: W77r

Specifications of W77E058A40PL

• Program Memory Type: FLASH
• Program Memory Size: 32KB (32K x 8)
• Core Processor: 8051
• Core Size: 8-Bit
• Speed: 40MHz
• Connectivity: EBI/EMI, Serial Port
• Peripherals: POR, WDT
• Number Of I /o: 36
• Ram Size: 1K x 8
• Voltage - Supply (vcc/vdd): 4.5 V ~ 5.5 V
• Oscillator Type: Internal
• Operating Temperature: 0°C ~ 70°C
• Package / Case: 44-PLCC
• Cpu Family: W77
• Device Core: 8051
• Device Core Size: 8b
• Frequency (max): 40MHz
• Interface Type: UART
• Total Internal Ram Size: 1KB
• # I/os (max): 32
• Number Of Timers - General Purpose: 3
• Operating Supply Voltage (typ): 5V
• Operating Supply Voltage (max): 5.5V
• Operating Supply Voltage (min): 4.5V
• Instruction Set Architecture: CISC
• Operating Temp Range: 0C to 70C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 44
• Package Type: PLCC
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Data Converters: -
• Lead Free Status / RoHS Status: Compliant, Lead free / RoHS Compliant

Slave Address Mask Enable
SADEN: This register enables the Automatic Address Recognition feature of the Serial port 0. When
Slave Address Mask Enable 1
SADEN1:This register enables the Automatic Address Recognition feature of the Serial port 1. When
Serial Port Control 1
SM0_1/FE_1: Serial port 1, Mode 0 bit or Framing Error Flag 1: The SMOD0 bit in PCON SFR
SM1_1: Serial port 1 Mode bit 1:
SM2_1: Multiple processors communication. Setting this bit to 1 enables the multiprocessor
communication feature in mode 2 and 3. In mode 2 or 3, if SM2_1 is set to 1, then RI_1 will
not be activated if the received 9th data bit (RB8_1) is 0. In mode 1, if SM2_1 = 1, then RI_1
will not be activated if a valid stop bit was not received. In mode 0, the SM2_1 bit controls the
serial port 1 clock. If set to 0, then the serial port 1 runs at a divide by 12 clock of the
oscillator. This gives compatibility with the standard 8052. When set to 1, the serial clock
Bit:
a bit in the SADEN is set to 1, the same bit location in SADDR will be compared with the
incoming serial data. When SADEN.n is 0, then the bit becomes a "don't care" in the
comparison. This register enables the Automatic Address Recognition feature of the Serial
port 0. When all the bits of SADEN are 0, interrupt will occur for any incoming address.
a bit in the SADEN1 is set to 1, the same bit location in SADDR1 will be compared with the
incoming serial data. When SADEN1.n is 0, then the bit becomes a "don't care" in the
comparison. This register enables the Automatic Address Recognition feature of the Serial
port 1. When all the bits of SADEN1 are 0, interrupt will occur for any incoming address.
determines whether this bit acts as SM0_1 or as FE_1. the operation of SM0_1 is
described below. When used as FE_1, this bit will be set to indicate an invalid stop bit.
This bit must be manually cleared in software to clear the FE_1 condition.
SM0_1/FE_1
Mnemonic: SADEN1
Mnemonic: SCON1
Mnemonic: SADEN
SM0_1 SM1_1 Mode
0
0
1
1
Bit:
Bit:
7
0
1
0
1
7
7
SM1_1
0
1
2
3
6
6
6
Description
Synchronous
Asynchronous
Asynchronous
Asynchronous
SM2_1
5
- 22 -
5
5
REN_1
4
Length
8
10
11
11
4
4
TB8_1
3
3
3
Address: BAh
RB8_1
Address: C0h
Address: B9h
Baud rate
4/12 Tclk
variable
64/32 Tclk
variable
2
2
2
TI_1
1
1
1
W77E58
RI_1
0
0
0