W77E058A40PL Nuvoton Technology Corporation of America, W77E058A40PL Datasheet - Page 24

• Manufacturer Part Number: W77E058A40PL
• Description: IC MCU 8-BIT 32K FLASH 44-PLCC
• Manufacturer: Nuvoton Technology Corporation of America
• Series: W77r

Specifications of W77E058A40PL

• Program Memory Type: FLASH
• Program Memory Size: 32KB (32K x 8)
• Core Processor: 8051
• Core Size: 8-Bit
• Speed: 40MHz
• Connectivity: EBI/EMI, Serial Port
• Peripherals: POR, WDT
• Number Of I /o: 36
• Ram Size: 1K x 8
• Voltage - Supply (vcc/vdd): 4.5 V ~ 5.5 V
• Oscillator Type: Internal
• Operating Temperature: 0°C ~ 70°C
• Package / Case: 44-PLCC
• Cpu Family: W77
• Device Core: 8051
• Device Core Size: 8b
• Frequency (max): 40MHz
• Interface Type: UART
• Total Internal Ram Size: 1KB
• # I/os (max): 32
• Number Of Timers - General Purpose: 3
• Operating Supply Voltage (typ): 5V
• Operating Supply Voltage (max): 5.5V
• Operating Supply Voltage (min): 4.5V
• Instruction Set Architecture: CISC
• Operating Temp Range: 0C to 70C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 44
• Package Type: PLCC
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Data Converters: -
• Lead Free Status / RoHS Status: Compliant, Lead free / RoHS Compliant

LIP: Low Priority Interrupt Status. When set, it indicates that software is servicing a low priority
XTUP:Crystal Oscillator Warm-up Status. when set, this bit indicates CPU has detected clock to be
SPTA1:Serial Port 1 Transmit Activity. This bit is set during serial port 1 is currently transmitting data.
SPRA1:Serial Port 1 Receive Activity. This bit is set during serial port 1 is currently receiving a data. It
SPTA0:Serial Port 0 Transmit Activity. This bit is set during serial port 0 is currently transmitting data.
SPRA0:Serial Port 0 Receive Activity. This bit is set during serial port 0 is currently receiving a data. It
Timed Access
TA: The Timed Access register controls the access to protected bits. To access protected bits, the
Timer 2 Control
TF2:
EXF2: Timer 2 External Flag: A negative transition on the T2EX pin (P1.1) or timer 2 overflow will
user must first write AAH to the TA. This must be immediately followed by a write of 55H to TA.
Now a window is opened in the protected bits for three machine cycles, during which the user can
write to these bits.
interrupt. This bit will be cleared when the program executes the corresponding RETI
instruction.
ready. Each time the crystal oscillator is restarted by exit from power down mode or the XTOFF
bit is set, hardware will clear this bit. This bit is set to 1 after a power-on reset. When this bit is
cleared, it prevents software from setting the XT/ RG bit to enable CPU operation from crystal
oscillator.
It is cleared
CD0,CD1 will be ignored when this bit is set to 1 and SWB = 1.
is cleared when RI_1 bit is set by hardware. Changing the Clock Divide Control bits CD0,CD1
will be ignored when this bit is set to 1 and SWB = 1.
It is cleared when TI bit is set by hardware. Changing the Clock Divide Control bits CD0,CD1
will be ignored when this bit is set to 1 and SWB = 1.
is cleared when RI bit is set by hardware. Changing the Clock Divide Control bits CD0,CD1
will be ignored when this bit is set to 1 and SWB = 1.
Timer 2 overflow flag: This bit is set when Timer 2 overflows. It is also set when the count is
equal to the capture register in down count mode. It can be set only if RCLK and TCLK are
both 0. It is cleared only by software. Software can also set or clear this bit.
cause this flag to set based on the CP RL
transition, this flag must be cleared by software. Setting this bit in software or detection of a
negative transition on T2EX pin will force a timer interrupt if enabled.
Mnemonic: TA
Mnemonic: T2CON
Bit:
Bit:
when TI_1 bit is set by hardware. Changing the Clock Divide Control bits
TF2
7
TA.7
7
EXF2
6
TA.6
6
RCLK
5
TA.5
- 24 -
5
/
2 , EXEN2 and DCEN bits. If set by a negative
TCLK
TA.4
4
4
EXEN2
TA.3
3
3
Address: C7h
Address: C8h
TR2
TA.2
2
2
W77E058A
C T
TA.1
/ 2
1
1
CP RL
TA.0
/
0
0
2