ST10F273M-4TR3 STMicroelectronics, ST10F273M-4TR3 Datasheet - Page 32

• Manufacturer Part Number: ST10F273M-4TR3
• Description: MCU 16BIT 512K FLASH 144-LQFP
• Manufacturer: STMicroelectronics
• Series: ST10r

Specifications of ST10F273M-4TR3

• Core Processor: ST10
• Core Size: 16-Bit
• Speed: 40MHz
• Connectivity: ASC, CAN, EBI/EMI, I²C, SSC, UART/USART
• Peripherals: POR, PWM, WDT
• Number Of I /o: 111
• Program Memory Size: 512KB (512K x 8)
• Program Memory Type: FLASH
• Ram Size: 36K x 8
• Voltage - Supply (vcc/vdd): 4.5 V ~ 5.5 V
• Data Converters: A/D 24x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 125°C
• Package / Case: 144-MQFP, 144-PQFP
• Processor Series: ST10F27x
• Core: ST10
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Details

Internal Flash memory
5.4.2
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Table 7.
Flash control register 0 high (FCR0H)
The Flash Control Register 0 High (FCR0H) together with the Flash Control Register 0 Low
(FCR0L) is used to enable and to monitor all the write operations on the IFlash. The user
has no access in write mode to the Test-Flash (B0TF). Moreover, the Test-Flash block is
seen by the user in Bootstrap mode only.
Table 8.
FCR0H (0x0E 0002)
WMS SUSP
Bit
3:2
Bit
RS
15
15
4
1
0
BSYNVR
RW
Name
14
Name
LOCK
WMS
-
-
WPG
RW
FCR0L register description (continued)
FCR0H register description
13
Write mode start
Flash registers access locked
Reserved. These bits must be left to their reset value (0).
Busy of Non-Volatile Registers
Reserved. This bit must be left to its reset value (0).
This bit must be set to start every write operation in the Flash module. At the end
of the write operation or during a Suspend, this bit is automatically reset. To
resume a suspended operation, this bit must be set again.
It is forbidden to set this bit if bit ERR of FER is high (the operation is not
accepted).
It is also forbidden to start a new write (program or erase) operation (by setting
WMS high) when bit SUSP of FCR0 is high. Resetting this bit by software has no
effect.
When this bit is set, it means that the access to the Flash Control Registers
FCR0H/-FCR1H/L, FDR0H/L-FDR1H/L, FARH/L and FER is locked by the FPEC:
any read access to the registers will output invalid data (software trap 009Bh) and
any write access will be ineffective. LOCK bit is automatically set when the Flash
bit WMS is set.
This is the only bit the user can always access to detect the status of the Flash:
once it is found low, the rest of FCR0L and all the other Flash registers are
accessible by the user as well.
Note that FER content can be read when LOCK is low, but its content is updated
only when also BSYx bits are reset.
This bit indicate that a write operation is running in the corresponding on “Non-
volatile registers”. They are automatically set when bit WMS is set. When this bit
is set every read access to the IFlash will output the value 009Bh (software trap),
while every write access to the IFlash will be ignored. At the end of the write
operation or during a Program Suspend this bit is automatically reset and the
IFlash returns to read mode. After a Program this bit is automatically set again.
DWPG
RW
12
RW
SER
11
10
Reserved
-
9
RW
SPR
8
FCR
MOD
RW
DS
7
Function
Function
6
5
4
Reserved
3
-
Reset value: 0000h
2
ST10F273M
1
0