C8051F312-GQR Silicon Laboratories Inc, C8051F312-GQR Datasheet - Page 189

• Manufacturer Part Number: C8051F312-GQR
• Description: IC 8051 MCU 8K FLASH 32LQFP
• Manufacturer: Silicon Laboratories Inc
• Series: C8051F31xr

Specifications of C8051F312-GQR

• Core Processor: 8051
• Core Size: 8-Bit
• Speed: 25MHz
• Connectivity: SMBus (2-Wire/I²C), SPI, UART/USART
• Peripherals: POR, PWM, Temp Sensor, WDT
• Number Of I /o: 29
• Program Memory Size: 8KB (8K x 8)
• Program Memory Type: FLASH
• Ram Size: 1.25K x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 3.6 V
• Data Converters: A/D 21x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 32-LQFP
• For Use With: 336-1445 - ADAPTER PROGRAM TOOLSTICK F310
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

17.1.2. Mode 1: 16-bit Counter/Timer
Mode 1 operation is the same as Mode 0, except that the counter/timer registers use all 16 bits. The coun-
ter/timers are enabled and configured in Mode 1 in the same manner as for Mode 0.
17.1.3. Mode 2: 8-bit Counter/Timer with Auto-Reload
Mode 2 configures Timer 0 and Timer 1 to operate as 8-bit counter/timers with automatic reload of the start
value. TL0 holds the count and TH0 holds the reload value. When the counter in TL0 overflows from all
ones to 0x00, the timer overflow flag TF0 (TCON.5) is set and the counter in TL0 is reloaded from TH0. If
Timer 0 interrupts are enabled, an interrupt will occur when the TF0 flag is set. The reload value in TH0 is
not changed. TL0 must be initialized to the desired value before enabling the timer for the first count to be
correct. When in Mode 2, Timer 1 operates identically to Timer 0.
Both counter/timers are enabled and configured in Mode 2 in the same manner as Mode 0. Setting the
TR0 bit (TCON.4) enables the timer when either GATE0 (TMOD.3) is logic 0 or when the input signal /INT0
is active as defined by bit IN0PL in register IT01CF (see
for details on the external input signals /INT0 and /INT1).
/INT0
T0
Crossbar
Pre-scaled Clock
SYSCLK
IN0PL
GATE0
Figure 17.2. T0 Mode 2 Block Diagram
XOR
0
1
TR0
M
H
T
3
M
T
3
L
CKCON
M
T
H
2
M
T
2
L
0
1
M
T
1
M
T
0
S
C
A
1
Rev. 1.7
S
C
A
0
G
A
T
E
1
C
T
1
/
C8051F310/1/2/3/4/5/6/7
M
T
1
1
TMOD
Section “8.3.2. External Interrupts” on page 95
M
T
1
0
TCLK
G
A
T
E
0
C
T
0
/
M
T
0
1
M
T
0
0
(8 bits)
(8 bits)
TH0
TL0
N
P
1
L
I
N
S
1
L
2
I
INT01CF
N
S
1
L
1
I
N
1
S
L
0
I
N
P
0
L
I
Reload
N
S
0
L
2
I
N
S
0
L
1
I
N
0
S
L
0
I
TR1
TR0
TF1
TF0
IE1
IE0
IT1
IT0
Interrupt
189