C8051F312-GQR Silicon Laboratories Inc, C8051F312-GQR Datasheet - Page 87

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C8051F312-GQR

Manufacturer Part Number
C8051F312-GQR
Description
IC 8051 MCU 8K FLASH 32LQFP
Manufacturer
Silicon Laboratories Inc
Series
C8051F31xr
Datasheets

Specifications of C8051F312-GQR

Core Processor
8051
Core Size
8-Bit
Speed
25MHz
Connectivity
SMBus (2-Wire/I²C), SPI, UART/USART
Peripherals
POR, PWM, Temp Sensor, WDT
Number Of I /o
29
Program Memory Size
8KB (8K x 8)
Program Memory Type
FLASH
Ram Size
1.25K x 8
Voltage - Supply (vcc/vdd)
2.7 V ~ 3.6 V
Data Converters
A/D 21x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
32-LQFP
For Use With
336-1445 - ADAPTER PROGRAM TOOLSTICK F310
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
C8051F312-GQR
Manufacturer:
Silicon Laboratories Inc
Quantity:
10 000
8.2.6. Special Function Registers
The direct-access data memory locations from 0x80 to 0xFF constitute the special function registers
(SFRs). The SFRs provide control and data exchange with the CIP-51's resources and peripherals. The
CIP-51 duplicates the SFRs found in a typical 8051 implementation as well as implementing additional
SFRs used to configure and access the sub-systems unique to the MCU. This allows the addition of new
functionality while retaining compatibility with the MCS-51™ instruction set. Table 8.2 lists the SFRs imple-
mented in the CIP-51 System Controller.
The SFR registers are accessed anytime the direct addressing mode is used to access memory locations
from 0x80 to 0xFF. SFRs with addresses ending in 0x0 or 0x8 (e.g. P0, TCON, SCON0, IE, etc.) are bit-
addressable as well as byte-addressable. All other SFRs are byte-addressable only. Unoccupied
addresses in the SFR space are reserved for future use. Accessing these areas will have an indeterminate
effect and should be avoided. Refer to the corresponding pages of the datasheet, as indicated in Table 8.3,
for a detailed description of each register.
D8 PCA0CN
D0
C8 TMR2CN
C0 SMB0CN
F8
F0
E8 ADC0CN PCA0CPL1 PCA0CPH1 PCA0CPL2 PCA0CPH2 PCA0CPL3 PCA0CPH3 RSTSRC
E0
B8
B0
A8
A0
98
90
88
80
(bit addressable)
SPI0CN
SCON0
TCON
PSW
ACC
0(8)
P3
P2
P1
P0
IP
IE
B
Table 8.2. Special Function Register (SFR) Memory Map
OSCXCN
SPI0CFG
PCA0MD PCA0CPM0 PCA0CPM1 PCA0CPM2
TMR3CN
REF0CN
SMB0CF
P0MDIN
CLKSEL
PCA0L
SBUF0
TMOD
XBR0
1(9)
SP
TMR2RLL
SMB0DAT
TMR3RLL
SPI0CKR
CPT1CN
OSCICN
P1MDIN
EMI0CN
AMX0N
PCA0H
XBR1
DPL
2(A)
TL0
PCA0CPL0 PCA0CPH0 PCA0CPL4 PCA0CPH4 VDM0CN
TMR2RLH
TMR3RLH
ADC0GTL ADC0GTH
SPI0DAT
CPT0CN
P2MDIN
OSCICL
AMX0P
DPH
3(B)
TL1
Rev. 1.7
C8051F310/1/2/3/4/5/6/7
P0MDOUT P1MDOUT P2MDOUT P3MDOUT
CPT1MD
ADC0CF
P3MDIN
P0SKIP
IT01CF
TMR2L
TMR3L
TH0
4(C)
PCA0CPM3 PCA0CPM4
ADC0LTL
CPT0MD
P1SKIP
TMR2H
TMR3H
ADC0L
TH1
5(D)
ADC0LTH
CPT1MX
CKCON
P2SKIP
ADC0H
FLSCL
EIP1
EIE1
6(E)
CPT0MX
PSCTL
FLKEY
PCON
7(F)
87

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