HD64F3672FPV Renesas Electronics America, HD64F3672FPV Datasheet - Page 105

• Manufacturer Part Number: HD64F3672FPV
• Description: IC H8/3672 MCU FLASH 64LQFP
• Manufacturer: Renesas Electronics America
• Series: H8® H8/300H Tinyr

Specifications of HD64F3672FPV

• Core Processor: H8/300H
• Core Size: 16-Bit
• Speed: 16MHz
• Connectivity: SCI
• Peripherals: PWM, WDT
• Number Of I /o: 26
• Program Memory Size: 16KB (16K x 8)
• Program Memory Type: FLASH
• Ram Size: 2K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 5.5 V
• Data Converters: A/D 4x10b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 64-LQFP
• For Use With: R0K436079S000BE - KIT DEV FOR H8/36079 W/COMPILER
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

DIVXS
2. Programming solution for DIVXS.W R0, ER1
Example: Convert dividend and divisor to non-negative numbers, then use DIVXU programming
solution for zero divide and overflow
L1: MOV.L
L2: MOV.W
L3: BTST
L4: RTS
ZERODIV:
DIVXS (DIVide eXtend as Signed)
MOV.W
BEQ
ANDC
BPL
NEG.W
ORC
BPL
NEG.L
XORC
EXTU.L
DIVXU.W
MOV.W
DIVXU.W
MOV.W
MOV.W
STC
BTST
BEQ
NEG.W
BEQ
NEG.L
R0, R0
ZERODIV
#AF, CCR
L1
R0
#10, CCR
ER1,ER1
L2
ER1
#50,CCR
E1, R2
ER2
R0, E2
E2, R1
R0, ER1
R2, E2
R1, R2
CCR, R1L
#6, R1L
L3
E1
#4, R1L
L4
ER2
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Test divisor
Branch to ZERODIV if R0 = 0
Clear CCR user bits (bits 6 and 4) to 0
Branch to L1 if N flag = 0 (positive divisor)
Take 2’s complement of R0 to make sign positive
Set CCR bit 4 to 1
Test dividend
Branch to L2 if N flag = 0 (positive dividend)
Take 2’s complement of ER1 to make sign positive
Invert CCR bits 6 and 4
Copy CCR contents to R1L
Test CCR bit 6
Branch to L3 if bit 6 = 1
Take 2’s complement of E1 to make sign of remainder negative
Test CCR bit 4
Branch to L4 if bit 4 = 1
Take 2’s complement of ER2 to make sign of quotient negative
Zero-divide handling routine
Use DIVXU.W instruction to divide non-negative dividend
by positive divisor
32 bits ÷ 16 bits
(16 bits)
(See DIVXU Instruction, Zero Divide, and Overflow)
Rev. 3.00 Dec 13, 2004 page 89 of 258
quotient (32 bits) and remainder
Section 2 Instruction Descriptions
REJ09B0213-0300
Divide Signed