DF36902GFHV Renesas Electronics America, DF36902GFHV Datasheet
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DF36902GFHV Summary of contents
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To our customers, Old Company Name in Catalogs and Other Documents st On April 1 , 2010, NEC Electronics Corporation merged with Renesas Technology Corporation, and Renesas Electronics Corporation took over all the business of both companies. Therefore, although the ...
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All information included in this document is current as of the date this document is issued. Such information, however, is subject to change without any prior notice. Before purchasing or using any Renesas Electronics products listed herein, please confirm ...
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H8/36912 Group, 16 H8/36902 Group Hardware Manual Renesas 16-Bit Single-Chip Microcomputer H8 Family/H8/300H Tiny Series The revision list can be viewed directly by clicking the title page. The revision list summarizes the locations of revisions and additions. Details should always ...
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Rev. 3.00 Sep. 14, 2006 Page ii of xxviii ...
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Keep safety first in your circuit designs! 1. Renesas Technology Corp. puts the maximum effort into making semiconductor products better and more reliable, but there is always the possibility that trouble may occur with them. Trouble with semiconductors may lead ...
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General Precautions on Handling of Product 1. Treatment of NC Pins Note: Do not connect anything to the NC pins. The NC (not connected) pins are either not connected to any of the internal circuitry or are used as test ...
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Configuration of This Manual This manual comprises the following items: 1. General Precautions on Handling of Product 2. Configuration of This Manual 3. Preface 4. Contents 5. Overview 6. Description of Functional Modules • CPU and System-Control Modules • On-Chip ...
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The H8/36912 Group and H8/36902 Group are single-chip microcomputers made up of the high- speed H8/300H CPU employing Renesas Technology original architecture as their cores, and the peripheral functions required to configure a system. The H8/300H CPU has an instruction ...
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Notes: When using an on-chip emulator (E7, E8) for H8/36912, H8/36902 program development and debugging, the following restrictions must be noted. 1. The NMI pin is reserved for the E7 or E8, and cannot be used. 2. Area H'2000 to ...
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Rev. 3.00 Sep. 14, 2006 Page viii of xxviii ...
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Section 1 Overview................................................................................................1 1.1 Features................................................................................................................................. 1 1.2 Internal Block Diagram......................................................................................................... 3 1.3 Pin Arrangement ................................................................................................................... 5 1.4 Pin Functions ........................................................................................................................ 9 Section 2 CPU......................................................................................................11 2.1 Address Space and Memory Map ....................................................................................... 12 2.2 Register Configuration........................................................................................................ 14 2.2.1 General Registers................................................................................................ 15 ...
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Interrupt Enable Register 2 (IENR2) .................................................................. 51 3.2.5 Interrupt Flag Register 1 (IRR1)......................................................................... 52 3.2.6 Interrupt Flag Register 2 (IRR2)......................................................................... 53 3.2.7 Wakeup Interrupt Flag Register (IWPR) ............................................................ 53 3.3 Reset Exception Handling .................................................................................................. 54 3.4 Interrupt Exception Handling ...
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Usage Notes ........................................................................................................................ 84 5.7.1 Note on Resonators............................................................................................. 84 5.7.2 Notes on Board Design ....................................................................................... 84 Section 6 Power-Down Modes ............................................................................85 6.1 Register Descriptions.......................................................................................................... 85 6.1.1 System Control Register 1 (SYSCR1) ................................................................ 86 6.1.2 System Control Register 2 (SYSCR2) ...
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Section 9 I/O Ports............................................................................................. 117 9.1 Port 1................................................................................................................................. 117 9.1.1 Port Mode Register 1 (PMR1) .......................................................................... 118 9.1.2 Port Control Register 1 (PCR1) ........................................................................ 119 9.1.3 Port Data Register 1 (PDR1) ............................................................................ 119 9.1.4 Port Pull-Up Control Register 1 (PUCR1)........................................................ ...
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Operation .......................................................................................................................... 142 10.3.1 Interval Timer Operation .................................................................................. 142 10.3.2 Auto-Reload Timer Operation .......................................................................... 142 10.4 Timer B1 Operating Modes .............................................................................................. 143 Section 11 Timer V............................................................................................145 11.1 Features............................................................................................................................. 145 11.2 Input/Output Pins.............................................................................................................. 147 11.3 Register Descriptions........................................................................................................ 147 11.3.1 Timer ...
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Timing of Counter Clearing by Compare Match .............................................. 183 12.5.5 Buffer Operation Timing .................................................................................. 184 12.5.6 Timing of IMFA to IMFD Flag Setting at Compare Match ............................. 185 12.5.7 Timing of IMFA to IMFD Setting at Input Capture ......................................... ...
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Multiprocessor Serial Data Transmission ......................................................... 229 14.6.2 Multiprocessor Serial Data Reception .............................................................. 231 14.7 Interrupts........................................................................................................................... 235 14.8 Usage Notes ...................................................................................................................... 236 14.8.1 Break Detection and Processing ....................................................................... 236 14.8.2 Mark State and Break Sending.......................................................................... 236 14.8.3 Receive Error Flags ...
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Section 16 A/D Converter ................................................................................. 273 16.1 Features............................................................................................................................. 273 16.2 Input/Output Pins.............................................................................................................. 275 16.3 Register Description ......................................................................................................... 275 16.3.1 A/D Data Registers (ADDRA to ADDRD) .......................................... 275 16.3.2 A/D Control/Status Register (ADCSR) ............................................................ 276 16.3.3 A/D Control ...
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Power Supply Voltage and Operating Ranges .................................................. 314 20.2.2 DC Characteristics ............................................................................................ 316 20.2.3 AC Characteristics ............................................................................................ 321 20.2.4 A/D Converter Characteristics .......................................................................... 325 20.2.5 Watchdog Timer Characteristics....................................................................... 326 20.2.6 Power-Supply-Voltage Detection Circuit Characteristics................................. 327 20.2.7 LVDI External Voltage ...
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Rev. 3.00 Sep. 14, 2006 Page xviii of xxviii ...
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Section 1 Overview Figure 1.1 Internal Block Diagram of H8/36912 Group................................................................. 3 Figure 1.2 Internal Block Diagram of H8/36902 Group................................................................. 4 Figure 1.3 Pin Arrangement of H8/36912 Group (FP-32A) ........................................................... 5 Figure 1.4 Pin Arrangement of H8/36902 Group (FP-32A) ........................................................... ...
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Section 5 Clock Pulse Generators Figure 5.1 Block Diagram of Clock Pulse Generators.................................................................. 69 Figure 5.2 State Transition of System Clock ................................................................................ 75 Figure 5.3 Flowchart of Clock Switching On-chip Oscillator Clock to External Clock (1) ........ 76 Figure 5.4 ...
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Figure 11.6 TMOV Output Timing ............................................................................................ 154 Figure 11.7 Clear Timing by Compare Match............................................................................ 154 Figure 11.8 Clear Timing by TMRIV Input ............................................................................... 155 Figure 11.9 Pulse Output Example ............................................................................................. 155 Figure 11.10 Example of Pulse Output Synchronized to TRGV ...
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Section 13 Watchdog Timer Figure 13.1 Block Diagram of Watchdog Timer ........................................................................ 191 Figure 13.2 Watchdog Timer Operation Example...................................................................... 195 Section 14 Serial Communication Interface 3 (SCI3) Figure 14.1 Block Diagram of SCI3........................................................................................... 198 Figure 14.2 Block Diagram of Noise ...
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Figure 15.8 Master Receive Mode Operation Timing (2)........................................................... 259 Figure 15.9 Slave Transmit Mode Operation Timing (1) ........................................................... 260 Figure 15.10 Slave Transmit Mode Operation Timing (2) ......................................................... 261 Figure 15.11 Slave Receive Mode Operation Timing (1)........................................................... 262 Figure 15.12 ...
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Figure 20.5 SCK3 Input Clock Timing ...................................................................................... 347 Figure 20.6 SCI3 Input/Output Timing in Clocked Synchronous Mode .................................... 348 Figure 20.7 Output Load Circuit ................................................................................................ 348 Appendix Figure B.1 Port 1 Block Diagram (P17) ..................................................................................... 379 Figure B.2 Port 1 ...
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Section 1 Overview Table 1.1 Pin Functions ............................................................................................................ 9 Section 2 CPU Table 2.1 Operation Notation ................................................................................................. 21 Table 2.2 Data Transfer Instructions....................................................................................... 22 Table 2.3 Arithmetic Operations Instructions (1) ................................................................... 23 Table 2.3 Arithmetic Operations Instructions (2) ................................................................... 24 ...
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Table 7.4 Reprogram Data Computation Table .................................................................... 109 Table 7.5 Additional-Program Data Computation Table ...................................................... 109 Table 7.6 Programming Time ............................................................................................... 109 Section 10 Timer B1 Table 10.1 Timer B1 Operating Modes .................................................................................. 143 Section 11 Timer V Table 11.1 ...
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Table 20.5 Serial Interface (SCI3) Timing ............................................................................. 324 Table 20.6 A/D Converter Characteristics .............................................................................. 325 Table 20.7 Watchdog Timer Characteristics........................................................................... 326 Table 20.8 Power-Supply-Voltage Detection Circuit Characteristics..................................... 327 Table 20.9 LVDI External Voltage Detection Circuit Characteristics.................................... 327 Table 20.10 Power-On ...
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Rev. 3.00 Sep. 14, 2006 Page xxviii of xxviii ...
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Features High-speed H8/300H central processing unit with an internal 16-bit architecture Upward-compatible with H8/300 CPU on an object level Sixteen 16-bit general registers 62 basic instructions Various peripheral functions Timer B1* (8-bit timer) Timer V (8-bit timer) Timer W ...
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Section 1 Overview General I/O ports Eighteen I/O pins, including five large-current ports ( mA Vcc 1 Four input only pins (also used for analog input) On-chip oscillator Frequency accuracy: (Flash memory ...
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Internal Block Diagram System clock generator P17/IRQ3/TRGV P14/IRQ0 P22/TXD P21/RXD P20/SCK3 P57/SCL P56/SDA P55/WKP5/ADTRG Note: * Can also be used for the emulator. Figure 1.1 Internal Block Diagram of H8/36912 Group On-chip CPU oscillator H8/300H Data ...
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Section 1 Overview System clock generator P17/IRQ3/TRGV P14/IRQ0 P22/TXD P21/RXD P20/SCK3 P57 P56 P55/WKP5/ADTRG Note: * Can also be used for the emulator. Figure 1.2 Internal Block Diagram of H8/36902 Group Rev. 3.00 Sep. 14, 2006 Page ...
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Pin Arrangement P84/FTIOD P74/TMRIV P75/TMCIV P76/TMOV PB3/AN3/ExtU PB2/AN2/ExtD PB1/AN1 PB0/AN0 Note: * Can also be used for the emulator. Figure 1.3 Pin Arrangement of H8/36912 Group (FP-32A H8/36912 Group (Top view) 29 ...
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Section 1 Overview P84/FTIOD P74/TMRIV P75/TMCIV P76/TMOV PB3/AN3/ExtU PB2/AN2/ExtD PB1/AN1 PB0/AN0 Note: * Can also be used for the emulator. Figure 1.4 Pin Arrangement of H8/36902 Group (FP-32A) Rev. 3.00 Sep. 14, 2006 Page 6 of 408 ...
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PB3/AN3/ExtU 1 PB2/AN2/ExtD 2 PB1/AN1 3 PB0/AN0 4 AVcc 5 Vcc 6 RES 7 TEST 8 Vss 9 PC1/OSC2/CLKOUT 10 PC0/OSC1 NMI 13 P17/IRQ3/TRGV 14 E10T_0* 15 E10T_1* 16 Note: * Can also be used for ...
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Section 1 Overview PB3/AN3/ExtU PB2/AN2/ExtD PB1/AN1 PB0/AN0 PC1/OSC2/CLKOUT PC0/OSC1 P17/IRQ3/TRGV E10T_0* E10T_1* Note: * Can also be used for the emulator. Figure 1.6 Pin Arrangement of H8/36902 Group (FP-32D, 32P4B) Rev. 3.00 Sep. 14, 2006 Page 8 ...
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Pin Functions Table 1.1 Pin Functions FP-32D, Type Symbol 32P4B Power source Clock OSC1 11 OSC2/ 10 CLKOUT RES System 7 control TEST 8 NMI External 13 ...
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Section 1 Overview FP-32D, Type Symbol 32P4B Timer V TMOV 32 TMCIV 31 TMRIV 30 TRGV 14 Timer W FTCI 25 FTIOA FTIOD bus SDA 19 interface 2* SCL 18 Serial TXD 24 ...
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This LSI has an H8/300H CPU with an internal 32-bit architecture that is upward-compatible with the H8/300 CPU, and supports only normal mode, which has a 64-kbyte address space. Upward-compatible with H8/300 CPUs Can execute H8/300 CPUs object programs Additional ...
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Section 2 CPU 2.1 Address Space and Memory Map The address space of this LSI is 64 kbytes, which includes the program area and the data area. The following two figures show the memory map, respectively. (Flash memory version) H'0000 ...
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H8/36911 H8/36901 (Masked ROM version) H'0000 Interrupt vector H'0045 H'0046 On-chip ROM (4 kbytes) H'0FFF Not used H'F600 Internal I/O register H'F77F Not used H'FE80 On-chip RAM user area (256 bytes) H'FF7F H'FF80 Internal I/O register H'FFFF Figure 2.1 Memory ...
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Section 2 CPU 2.2 Register Configuration The H8/300H CPU has the internal registers shown in figure 2.2. There are two types of registers; general registers and control registers. The control registers are a 24-bit program counter (PC), and an 8-bit ...
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General Registers The H8/300H CPU has eight 32-bit general registers. These general registers are all functionally identical and can be used as both address registers and data registers. When a general register is used as a data register, it ...
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Section 2 CPU General register ER7 has the function of stack pointer (SP) in addition to its general-register function, and is used implicitly in exception handling and subroutine calls. Figure 2.4 shows the stack. SP (ER7) Figure 2.4 Relationship between ...
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Initial Bit Bit Name Value Undefined R Undefined R Undefined R Undefined R Undefined R Undefined R Undefined R/W R/W Description R/W Interrupt ...
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Section 2 CPU 2.3 Data Formats The H8/300H CPU can process 1-bit, 4-bit (BCD), 8-bit (byte), 16-bit (word), and 32-bit (longword) data. Bit-manipulation instructions operate on 1-bit data by accessing bit … ...
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Data Type General Data Format Register Word data Rn Word data En 15 MSB Longword ERn data 31 MSB [Legend] ERn: General register ER En: General register E Rn: General register R RnH: General register RH RnL: General register RL ...
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Section 2 CPU 2.3.2 Memory Data Formats Figure 2.6 shows the data formats in memory. The H8/300H CPU can access word data and longword data in memory, however word or longword data must begin at an even address ...
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Instruction Set 2.4.1 Table of Instructions Classified by Function The H8/300H CPU has 62 instructions. Tables 2.2 to 2.9 summarize the instructions in each functional category. The notation used in tables 2.2 to 2.9 is defined below. Table 2.1 ...
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Section 2 CPU Symbol Description :3/:8/:16/:24 3-, 8-, 16-, or 24-bit length Note: General registers include 8-bit registers (R0H to R7H, R0L to R7L), 16-bit registers ( R7 E7), and 32-bit registers/address registers (ER0 to ER7). ...
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Table 2.3 Arithmetic Operations Instructions (1) Instruction Size* Function ADD B/W/L Rd ± Rs SUB Performs addition or subtraction on data in two general registers immediate data and data in a general register (immediate byte data cannot be ...
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Section 2 CPU Table 2.3 Arithmetic Operations Instructions (2) Instruction Size* Function DIVXS B/W Rd ÷ Rs Performs signed division on data in two general registers: either 16 bits ÷ 8 bits quotient and 16-bit remainder. CMP B/W/L Rd – ...
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Table 2.4 Logic Operations Instructions Instruction Size* Function AND B/W/L Rd Performs a logical AND operation on a general register and another general register or immediate data. OR B/W/L Rd Performs a logical OR operation on a general register and ...
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Section 2 CPU Table 2.6 Bit Manipulation Instructions (1) Instruction Size* Function BSET B 1 Sets a specified bit in a general register or memory operand to 1. The bit number is specified by 3-bit immediate data or the lower ...
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Table 2.6 Bit Manipulation Instructions (2) Instruction Size* Function BXOR B C XORs the carry flag with a specified bit in a general register or memory operand and stores the result in the carry flag. BIXOR B C XORs the ...
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Section 2 CPU Table 2.7 Branch Instructions Instruction Size Function Bcc* — Branches to a specified address if a specified condition is true. The branching conditions are listed below. Mnemonic BRA(BT) BRN(BF) BHI BLS BCC(BHS) BCS(BLO) BNE BEQ BVC BVS ...
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Table 2.8 System Control Instructions Instruction Size* Function TRAPA — Starts trap-instruction exception handling. RTE — Returns from an exception-handling routine. SLEEP — Causes a transition to a power-down state. LDC B/W (EAs) Moves the source operand contents to the ...
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Section 2 CPU Table 2.9 Block Data Transfer Instructions Instruction Size Function EEPMOV.B — if R4L else next; EEPMOV.W — else next; Transfers a data block. Starting from the address set in ER5, transfers data for the number ...
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Effective Address Extension 8, 16 bits specifying immediate data, an absolute address displacement. A24-bit address or displacement is treated as a 32-bit data in which the first 8 bits are 0 (H'00). (4) Condition Field ...
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Section 2 CPU 2.5 Addressing Modes and Effective Address Calculation The following describes the H8/300H CPU. In this LSI, the upper eight bits are ignored in the generated 24-bit address, so the effective address is 16 bits. 2.5.1 Addressing Modes ...
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Register Indirect—@ERn The register field of the instruction code specifies an address register (ERn), the lower 24 bits of which contain the address of the operand on memory. (3) Register Indirect with Displacement—@(d:16, ERn) or @(d:24, ERn) A 16-bit ...
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Section 2 CPU Table 2.11 Absolute Address Access Ranges Absolute Address 8 bits (@aa:8) 16 bits (@aa:16) 24 bits (@aa:24) (6) Immediate—#xx:8, #xx:16, or #xx:32 The instruction contains 8-bit (#xx:8), 16-bit (#xx:16), or 32-bit (#xx:32) immediate data as an operand. ...
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Figure 2.8 Branch Address Specification in Memory Indirect Mode 2.5.2 Effective Address Calculation Table 2.12 indicates how effective addresses are calculated in each addressing mode. In this LSI, the upper 8 bits of the effective address are ignored in order ...
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Section 2 CPU Table 2.12 Effective Address Calculation (2) Addressing Mode and Instruction Format Absolute address Immediate [Legend] r, rm,rn : Register field op : Operation field disp : Displacement IMM : Immediate data abs : Absolute address Rev. 3.00 ...
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Basic Bus Cycle CPU operation is synchronized by a system clock ( ). The period from a rising edge of to the next rising edge is called one state. A bus cycle consists of two states or three states. ...
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Section 2 CPU 2.6.2 On-Chip Peripheral Modules On-chip peripheral modules are accessed in two states or three states. The data bus width is 8 bits or 16 bits depending on the register. For description on the data bus width and ...
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CPU States There are four CPU states: the reset state, program execution state, program halt state, and exception-handling state. The program execution state includes active mode. In the program halt state there are a sleep mode, and standby mode. ...
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Section 2 CPU Reset state Reset occurs Program halt state 2.8 Usage Notes 2.8.1 Notes on Data Access to Empty Areas The address space of this LSI includes empty areas in addition to the ROM, RAM, and on-chip I/O registers ...
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Bit Manipulation for Two Registers Assigned to the Same Address Example 1: Bit manipulation for the timer load register and timer counter (Applicable to timer B1, not available for the H8/36902 Group.) Figure 2.13 shows an example of a ...
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Section 2 CPU Example 2: The BSET instruction is executed for port 5. P57 and P56 are input pins, with a low-level signal input at P57 and a high-level signal input at P56. P55 to P50 are output pins and ...
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As a result of the BSET instruction, bit 0 in PDR5 becomes 1, and P50 outputs a high-level signal. However, bits 7 and 6 of PDR5 end up with different values. To prevent this problem, store a copy of the ...
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Section 2 CPU (2) Bit Manipulation in a Register Containing a Write-Only Bit Example 3: BCLR instruction executed designating port 5 control register PCR5 P57 and P56 are input pins, with a low-level signal input at P57 and a high-level ...
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As a result of this operation, bit 0 in PCR5 becomes 0, making P50 an input port. However, bits 7 and 6 in PCR5 change that P57 and P56 change from input pins to output pins. To ...
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Section 2 CPU Rev. 3.00 Sep. 14, 2006 Page 46 of 408 REJ09B0105-0300 ...
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Section 3 Exception Handling Exception handling may be caused by a reset, a trap instruction (TRAPA), or interrupts. Reset A reset has the highest exception priority. Exception handling starts as soon as the reset is cleared by the RES pin. ...
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Section 3 Exception Handling Relative Module Exception Sources Address break Break conditions satisfied CPU Direct transition by executing the SLEEP instruction External interrupt IRQ0, low-voltage detection pin interrupt Reserved for system use External interrupt IRQ3 pin WKP Reserved for system ...
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Register Descriptions Interrupts are controlled by the following registers. Interrupt edge select register 1 (IEGR1) Interrupt edge select register 2 (IEGR2) Interrupt enable register 1 (IENR1) Interrupt enable register 2 (IENR2) Interrupt flag register 1 (IRR1) Interrupt flag register ...
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Section 3 Exception Handling 3.2.2 Interrupt Edge Select Register 2 (IEGR2) IEGR2 selects the direction of an edge that generates interrupt requests of the ADTRG and WKP5 pins. Initial Bit Bit Name Value 7, 6 All 1 5 WPEG5 0 ...
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Initial Bit Bit Name Value 0 IEN0 0 3.2.4 Interrupt Enable Register 2 (IENR2) IENR2 enables timer B1 interrupts. Initial Bit Bit Name Value IENTB1 All 1 When disabling interrupts by ...
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Section 3 Exception Handling 3.2.5 Interrupt Flag Register 1 (IRR1) IRR1 is a status flag register for direct transition interrupts, and IRQ3 and IRQ0 interrupt requests. Initial Bit Bit Name Value 7 IRRDT All 1 ...
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Interrupt Flag Register 2 (IRR2) IRR2 is a status flag register for timer B1 interrupt requests. Initial Bit Bit Name Value IRRTB1 All 1 3.2.7 Wakeup Interrupt Flag Register (IWPR) IWPR ...
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Section 3 Exception Handling 3.3 Reset Exception Handling When the RES pin goes low, all processing halts and this LSI enters the reset. The internal state of the CPU and the registers of the on-chip peripheral modules are initialized by ...
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Interrupt Exception Handling 3.4.1 External Interrupts As external interrupts, there are NMI, IRQ3, IRQ0, and WKP5 interrupts. (1) NMI Interrupt NMI interrupt is requested by input falling edge to the NMI pin. NMI is the highest interrupt, and can ...
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Section 3 Exception Handling RES φ Internal address bus Internal read signal Internal write signal Internal data bus (16 bits) (1) Reset exception handling vector address (H'0000) (2) Program start address (3) Initial program instruction 3.4.2 Internal Interrupts Each on-chip ...
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Interrupt Handling Sequence Interrupts are controlled by an interrupt controller. Interrupt operation is described as follows interrupt occurs while the NMI or interrupt enable bit is set interrupt request signal is sent to ...
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Section 3 Exception Handling Figure 3.3 shows a typical interrupt sequence where the program area is in the on-chip ROM and the stack area is in the on-chip RAM. RES φ Internal address bus Internal read signal Internal write signal ...
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Interrupt Response Time Table 3.2 shows the number of wait states after an interrupt request flag is set until the first instruction of the interrupt handling-routine is executed. Table 3.2 Interrupt Wait States Item Waiting time for completion of ...
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Section 3 Exception Handling Rev. 3.00 Sep. 14, 2006 Page 60 of 408 REJ09B0105-0300 Figure 3.3 Interrupt Sequence ...
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Usage Notes 3.5.1 Interrupts after Reset If an interrupt is accepted after a reset and before the stack pointer (SP) is initialized, the PC and CCR will not be saved correctly, leading to a program crash. To prevent this, ...
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Section 3 Exception Handling Rev. 3.00 Sep. 14, 2006 Page 62 of 408 REJ09B0105-0300 ...
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Section 4 Address Break The address break simplifies on-board program debugging. It requests an address break interrupt when the set break condition is satisfied. The interrupt request is not affected by the I bit of CCR. Break conditions that can ...
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Section 4 Address Break 4.1 Register Descriptions Address break has the following registers. Address break control register (ABRKCR) Address break status register (ABRKSR) Break address register (BARH, BARL) Break data register (BDRH, BDRL) 4.1.1 Address Break Control Register (ABRKCR) ABRKCR ...
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Initial Bit Bit Name Value 1 DCMP1 0 0 DCMP0 0 [Legend] X: Don't care When an address break is set in the data read cycle or data write cycle, the data bus used will depend on the combination of ...
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Section 4 Address Break 4.1.2 Address Break Status Register (ABRKSR) ABRKSR consists of the address break interrupt flag and the address break interrupt enable bit. Initial Bit Bit Name Value 7 ABIF 0 6 ABIE — ...
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Operation When the ABIF and ABIE bits in ABRKSR are set to 1, the address break function generates an interrupt request to the CPU. The ABIF bit in ABRKSR is set the combination of the address ...
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Section 4 Address Break When the address break is specified in the data read cycle Register setting • ABRKCR = H'A0 • BAR = H'025A MOV instruc- tion 1 prefetch φ Address 025C bus Interrupt request Figure 4.2 Address Break ...
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Section 5 Clock Pulse Generators Clock oscillator circuitry (CPG: clock pulse generator) consists of an external oscillator, an on- chip oscillator, a duty correction circuit, a clock select circuit, and system clock dividers. Figure 5.1 shows a block diagram of ...
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Section 5 Clock Pulse Generators 5.1 Features Choice of two clock sources On-chip oscillator clock External oscillator clock Choice of two types of on-chip oscillation frequency by the user software 8MHz 10MHz Frequency trimming Users can adjust the on-chip oscillation ...
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Register Descriptions Clock oscillators are controlled by the following registers. RC control register (RCCR) RC trimming data protect register (RCTRMDPR) RC trimming data register (RCTRMDR) Clock control/status register (CKCSR) 5.2.1 RC Control Register (RCCR) RCCR controls the on-chip oscillator. ...
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Section 5 Clock Pulse Generators 5.2.2 RC Trimming Data Protect Register (RCTRMDPR) RCTRMDPR controls RCTRMDPR itself and writing to RCTRMDR. Use the MOV instruction to rewrite this register. Bit manipulation instruction cannot change the settings. Initial Bit Bit Name Value ...
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Initial Bit Bit Name Value 4 0 TRMDRWE All 1 5.2.3 RC Trimming Data Register (RCTRMDR) RCTRMDR stores the trimming data of the on-chip oscillator frequency. Initial Bit Bit Name Value 7 TRMD7 (0)* 6 TRMD6 (0)* ...
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Section 5 Clock Pulse Generators 5.2.4 Clock Control/Status Register (CKCSR) CKCSR selects the port C function, controls switching the system clocks, and indicates the system clock state. Initial Bit Bit Name Value 7 PMRC1 0 6 PMRC0 ...
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System Clock Select Operation Figure 5.2 shows the state transition of the system clock. Reset state On-chip oscillator: Halted External oscillator: Operated Figure 5.2 State Transition of System Clock LSI operates on on-chip oscillator clock Reset release On-chip oscillator: ...
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Section 5 Clock Pulse Generators 5.3.1 Clock Control Operation The LSI system clock is generated by the on-chip oscillator clock after a reset. The on-chip oscillator clock is switched to the external clock by the user software. LSI operates on ...
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LSI operates on external clock Start (LSI operates on external clock) Write 0 to RCSTP in RCCR Write 1 to CKSWIE in CKCSR if necessary Write 0 to OSCSEL in CKCSR LSI operates on on-chip oscillator clock When CKSWIE = ...
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Section 5 Clock Pulse Generators 5.3.2 Clock Change Timing The timing for changing clocks are shown in figures 5.5 and 5.6. OSC RC OSCSEL PHISTOP (Internal signal) CKSTA On-chip oscillator clock operation Wait for external oscillation settling [Legend] OSC: External ...
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OSC RC OSCSEL PHISTOP (Internal signal) CKSTA CKSWIF External clock operation Wait for external oscillation settling [Legend] OSC: External clock RC: On-chip oscillator clock : System clock OSCSEL: Bit 4 in CKCSR PHISTOP: System clock stop control signal CKSTA: Bit ...
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Section 5 Clock Pulse Generators 5.4 Trimming of On-chip Oscillator Frequency Users can trim the on-chip oscillator frequency, supplying the external reference pulses with the input capture function in internal timer W. An example of trimming flow and a timing ...
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RC FTIOA input capture input Timer TCNT GRA N GRC Capture 1 Figure 5.8 Timing Chart of Trimming of On-chip Oscillator Frequency The on-chip oscillator frequency is gained by the expression below. ...
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Section 5 Clock Pulse Generators 5.5 External Oscillators This LSI has two methods to supply external clock pulses into it: connecting a crystal or ceramic resonator, and an external clock. Oscillation pins OSC1 and OSC2 are common with general ports ...
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Connecting Ceramic Resonator Figure 5.11 shows an example of connecting a ceramic resonator. PC0/OSC1 PC1/OSC2/CLKOUT Figure 5.11 Example of Connection to Ceramic Resonator 5.5.3 External Clock Input Method To use the external clock, input the external clock on pin ...
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Section 5 Clock Pulse Generators 5.7 Usage Notes 5.7.1 Note on Resonators Resonator characteristics are closely related to board design and should be carefully evaluated by the user, referring to the examples shown in this section. Resonator circuit parameters will ...
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Section 6 Power-Down Modes For operating modes after a reset, this LSI has not only a normal active mode but also three power-down modes in which power consumption is significantly reduced. In addition, there is also a module standby function ...
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Section 6 Power-Down Modes 6.1.1 System Control Register 1 (SYSCR1) SYSCR1 controls the power-down modes, as well as SYSCR2. Initial Bit Bit Name Value 7 SSBY 0 6 STS2 0 5 STS1 0 4 STS0 All ...
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Table 6.1 Operating Frequency and Wait Time Bit Name STS2 STS1 STS0 Wait Time 8,192 states 16,384 states 32,768 states 65,536 states 131,072 states 1 ...
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Section 6 Power-Down Modes 6.1.2 System Control Register 2 (SYSCR2) SYSCR2 controls the power-down modes, as well as SYSCR1. Initial Bit Bit Name Value 7 SMSEL DTON 0 4 MA2 0 3 MA1 0 2 MA0 ...
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Module Standby Control Register 1 (MSTCR1) MSTCR1 allows the on-chip peripheral modules to enter a standby state in module units. Initial Bit Bit Name Value MSTIIC 0 5 MSTS3 0 4 MSTAD 0 3 MSTWD 0 ...
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Section 6 Power-Down Modes 6.1.4 Module Standby Control Register 2 (MSTCR2) MSTCR2 allows the on-chip peripheral modules to enter a standby state in module units. Initial Bit Bit Name Value All 0 4 MSTTB1 ...
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Mode Transitions and States of LSI Figure 6.1 shows the possible transitions among these operating modes. A transition is made from the program execution state to the program halt state of the program by executing a SLEEP instruction. Interrupts ...
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Section 6 Power-Down Modes Table 6.2 Transition Mode after SLEEP Instruction Execution and Interrupt Handling DTON SSBY SMSEL [Legend] X: Don’t care Note: When a state transition is performed while ...
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Sleep Mode In sleep mode, CPU operation is halted but the on-chip peripheral modules function at the clock frequency set by the MA2 to MA0 bits in SYSCR2. CPU register contents are retained. When an interrupt is requested, sleep ...
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Section 6 Power-Down Modes 6.2.3 Subsleep Mode In subsleep mode, the system clock oscillator is halted, and operation of the CPU and on-chip peripheral modules is halted. However, as long as the rated voltage is supplied, the contents of CPU ...
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Module Standby Function The module standby function can be set to any peripheral module. In module standby mode, the clock supply to the specified module stops and the module enters the power-down mode. Module standby mode enables each on-chip ...
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Section 6 Power-Down Modes Rev. 3.00 Sep. 14, 2006 Page 96 of 408 REJ09B0105-0300 ...
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The features of the 12-kbyte (including 4 kbytes as the control program area) flash memory built into the HD64F36912G and HD64F36902G are summarized below. Programming/erase methods The flash memory is programmed in 64-byte units at a time. ...
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Section 7 ROM H'0000 H'0001 Erase unit H'0040 H'0041 1 kbyte H'03C0 H'03C1 H'0400 H'0401 Erase unit H'0440 H'0441 1 kbyte H'07C0 H'07C1 H'0800 H'0801 Erase unit H'0840 H'0841 1 kbyte H'0BC0 H'0BC1 H'0C00 H'0C01 Erase unit H'0C40 H'0C41 1 ...
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Register Descriptions The flash memory has the following registers. Flash memory control register 1 (FLMCR1) Flash memory control register 2 (FLMCR2) Erase block register 1 (EBR1) Flash memory enable register (FENR) 7.2.1 Flash Memory Control Register 1 (FLMCR1) FLMCR1 ...
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Section 7 ROM Initial Bit Bit Name Value 7.2.2 Flash Memory Control Register 2 (FLMCR2) FLMCR2 is a register that displays the state of flash memory programming/erasing. FLMCR2 is a read-only ...
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Erase Block Register 1 (EBR1) EBR1 specifies the flash memory erase area block. EBR1 is initialized to H'00 when the SWE bit in FLMCR1 not set more than one bit at a time, as this will ...
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Section 7 ROM 7.3 On-Board Programming Modes There is a mode for programming/erasing of the flash memory; boot mode, which enables on- board programming/erasing. On-board programming/erasing can also be performed in user program mode. At reset-start in reset mode, this ...
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When the boot program is initiated, the chip measures the low-level period of asynchronous SCI communication data (H'00) transmitted continuously from the host. The chip then calculates the bit rate of transmission from the host, and adjusts the SCI3 ...
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Section 7 ROM Table 7.2 Boot Mode Operation Host Operation Processing Contents Continuously transmits data H'00 at specified bit rate. Transmits data H'55 when data H'00 is received error-free. Boot program erase error H'AA reception Transmits number of bytes (N) ...
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Table 7.3 System Clock Frequencies for which Automatic Adjustment of LSI Bit Rate is Possible Host Bit Rate System Clock Frequency Range of LSI 9,600 bps 8 MHz (on-chip oscillator clock) 4,800 bps 8 MHz (on-chip oscillator clock) 2,400 bps ...
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Section 7 ROM 7.3.2 Programming/Erasing in User Program Mode On-board programming/erasing of an individual flash memory block can also be performed in user program mode by branching to a user program/erase control program. The user must set branching conditions and ...
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Flash Memory Programming/Erasing A software method using the CPU is employed to program and erase flash memory in the on- board programming modes. Depending on the FLMCR1 setting, the flash memory operates in one of the following four modes: ...
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Section 7 ROM Write pulse application subroutine Apply Write Pulse WDT enable Set PSU bit in FLMCR1 Wait 50 s Set P bit in FLMCR1 Wait (Wait time = Programming time) Clear P bit in FLMCR1 Wait 5 s Clear ...
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Table 7.4 Reprogram Data Computation Table Program Data Verify Data Table 7.5 Additional-Program Data Computation Table Reprogram Data Verify Data Table 7.6 Programming Time ...
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Section 7 ROM 6. If the read data is not erased successfully, set erase mode again, and repeat the erase/erase- verify sequence as before. The maximum number of repetitions of the erase/erase-verify sequence is 100. 7.4.3 Interrupt Handling when Programming/Erasing ...
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Set block start address as verify address H'FF dummy write to verify address Increment address No No All erase block erased ? Notes: 1. The RTS instruction must not be used during a period between dummy writing of H'FF to ...
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Section 7 ROM 7.5 Program/Erase Protection There are three kinds of flash memory program/erase protection; hardware protection, software protection, and error protection. 7.5.1 Hardware Protection Hardware protection refers to a state in which programming/erasing of flash memory is forcibly disabled ...
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The FLMCR1, FLMCR2, and EBR1 settings are retained, however program mode or erase mode is aborted at the point at which the error occurred. Program mode or erase mode cannot be re- entered by re-setting the bit. ...
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Section 7 ROM Rev. 3.00 Sep. 14, 2006 Page 114 of 408 REJ09B0105-0300 ...
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The H8/36912F and H8/36902F have 1536 bytes, the H8/36912 and H8/36902 have 512 bytes, and the H8/36911, H8/36901, and H8/36900 have 256 bytes of on-chip high-speed static RAM, respectively. The RAM is connected to the CPU by a 16-bit data ...
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Section 8 RAM Rev. 3.00 Sep. 14, 2006 Page 116 of 408 REJ09B0105-0300 ...
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The LSI of the H8/36912 Group and H8/36902 Group has 18 general I/O ports. Port 8 (P84 to P80 large current port, which can drive 20 mA (@V output. Any of these ports can become an input port ...
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Section 9 I/O Ports 9.1.1 Port Mode Register 1 (PMR1) PMR1 switches the functions of pins in port 1 and port 2. Initial Bit Bit Name Value 7 IRQ3 All 0 4 IRQ0 All ...
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Port Control Register 1 (PCR1) PCR1 selects inputs/outputs in bit units for pins to be used as general I/O ports of port 1. Initial Bit Bit Name Value 7 PCR17 PCR14 ...
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Section 9 I/O Ports 9.1.4 Port Pull-Up Control Register 1 (PUCR1) PUCR1 controls the pull-up MOS in bit units of the pins set as the input ports. Initial Bit Bit Name Value 7 PUCR17 ...
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P14/IRQ0 pin Register PMR1 PCR1 Bit Name IRQ0 PCR14 Setting value [Legend] X: Don't care 9.2 Port 2 Port general I/O port also functioning as a SCI3 I/O pin. Each pin of ...
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Section 9 I/O Ports 9.2.1 Port Control Register 2 (PCR2) PCR2 selects inputs/outputs in bit units for pins to be used as general I/O ports of port 2. Initial Bit Bit Name Value PCR22 0 1 ...
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Pin Functions The correspondence between the register specification and the port functions is shown below. P22/TXD pin Register PMR1 PCR2 Bit Name TXD PCR22 Setting 0 0 value [Legend] X: Don't care P21/RXD pin Register SCR3 ...
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Section 9 I/O Ports 9.3 Port 5 Port general I/O port also functioning and wakeup interrupt input pin. Each pin of the port 5 is shown in figure 9.3. The register setting 2 of ...
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Port Mode Register 5 (PMR5) PMR5 switches the functions of pins in port 5. Initial Bit Bit Name Value 7, 6 All 0 5 WKP5 All 0 9.3.2 Port Control Register 5 (PCR5) PCR5 selects ...
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Section 9 I/O Ports 9.3.3 Port Data Register 5 (PDR5) PDR5 is a general I/O port data register of port 5. Initial Bit Bit Name Value 7 P57 0 6 P56 0 5 P55 All 1 ...
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Pin Functions The correspondence between the register specification and the port functions is shown below. P57/SCL pin Register ICCR PCR5 Bit Name ICE PCR57 Setting value [Legend] X: Don't care Note: As the SCL ...
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Section 9 I/O Ports 9.4 Port 7 Port general I/O port also functioning as a timer V I/O pin. Each pin of the port 7 is shown in figure 9.4. The register setting of TCSRV in timer ...
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Port Data Register 7 (PDR7) PDR7 is a general I/O port data register of port 7. Initial Bit Bit Name Value P76 0 5 P75 0 4 P74 All 1 9.4.3 Pin ...
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Section 9 I/O Ports P75/TMCIV pin Register PCR7 Bit Name PCR75 Pin Function Setting value 0 P75 input/TMCIV input pin 1 P75 output/TMCIV input pin P74/TMRIV pin Register PCR7 Bit Name PCR74 Pin Function Setting value 0 P74 input/TMRIV input ...
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Port Control Register 8 (PCR8) PCR8 selects inputs/outputs in bit units for pins to be used as general I/O ports of port 8. Initial Bit Bit Name Value PCR84 0 3 PCR83 0 2 PCR82 ...
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Section 9 I/O Ports 9.5.3 Pin Functions The correspondence between the register specification and the port functions is shown below. P84/FTIOD pin Register TMRW Bit Name PWMD IOD2 Setting 0 0 value [Legend] X: Don't ...
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P82/FTIOB pin Register TMRW Bit Name PWMB IOB2 Setting 0 0 value [Legend] X: Don't care P81/FTIOA pin Register TIOR0 Bit Name IOA2 IOA1 Setting value [Legend] ...
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Section 9 I/O Ports 9.6 Port B Port input port also functioning as an A/D converter analog input pin and LVD external comparison voltage input pin. Each pin of the port B is shown in figure 9.6. ...
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Pin Functions The correspondence between the register specification and the port functions is shown below. PB3/AN3/ExtU pin Register Bit Name CH2 CH1 Setting value 0 1 Other than the above values PB2/AN2/ExtD pin Register Bit Name CH2 SCAN Setting ...
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Section 9 I/O Ports PB0/AN0 pin Register Bit Name CH2 SCAN Setting 0 0 value 0 1 Other than the above values [Legend] X: Don't care 9.7 Port C Port general I/O port also functioning as an ...
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Port Control Register C (PCRC) PCRC selects inputs/outputs in bit units for pins to be used as general I/O ports of port C. Initial Bit Bit Name Value PCRC1 0 0 PCRC0 0 9.7.2 Port ...
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Section 9 I/O Ports 9.7.3 Pin Functions The correspondence between the register specification and the port functions is shown below. PC1/OSC2/CLKOUT pin Register Bit Name PMRC1 Setting value 0 1 [Legend] X: Don't care PC0/OSC1 pin Register CKCSR Bit Name ...
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Timer 8-bit timer that increments each time a clock pulse is input. This timer has two operating modes, interval and auto reload. Figure 10.1 shows a block diagram of timer B1. 10.1 Features Selection of seven internal ...
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Section 10 Timer B1 10.2 Register Descriptions The timer B1 has the following registers. Timer mode register B1 (TMB1) Timer counter B1 (TCB1) Timer load register B1 (TLB1) 10.2.1 Timer Mode Register B1 (TMB1) TMB1 selects the auto-reload function and ...
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Timer Counter B1 (TCB1) TCB1 is an 8-bit read-only up-counter, which is incremented by internal clock input. The clock source for input to this counter is selected by bits TMB12 to TMB10 in TMB1. TCB1 values can be read ...
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Section 10 Timer B1 10.3 Operation 10.3.1 Interval Timer Operation When bit TMB17 in TMB1 is cleared to 0, timer B1 functions as an 8-bit interval timer. Upon reset, TCB1 is cleared to H'00 and bit TMB17 is cleared to ...
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Timer B1 Operating Modes Table 10.1 shows the timer B1 operating modes. Table 10.1 Timer B1 Operating Modes Operating Mode Reset TCB1 Interval Reset Auto-reload Reset TMB1 Reset Active Sleep Functions Functions Functions Functions Functions Retained Rev. 3.00 Sep. ...
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Section 10 Timer B1 Rev. 3.00 Sep. 14, 2006 Page 144 of 408 REJ09B0105-0300 ...
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Timer 8-bit timer based on an 8-bit counter. Timer V counts external events. Compare- match signals with two registers can also be used to reset the counter, request an interrupt, or output a pulse signal with an ...
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Section 11 Timer V TRGV Clock select TMCIV φ PSS TMRIV TMOV [Legend] TCORA: Time constant register A TCORB: Time constant register B TCNTV: Timer counter V TCSRV: Timer control/status register V TCRV0: Timer control register V0 TCRV1: Timer control ...
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Input/Output Pins Table 11.1 shows the timer V pin configuration. Table 11.1 Pin Configuration Name Timer V output Timer V clock input Timer V reset input Trigger input 11.3 Register Descriptions Time V has the following registers. Timer counter ...
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Section 11 Timer V 11.3.2 Time Constant Registers A and B (TCORA, TCORB) TCORA and TCORB have the same function. TCORA and TCORB are 8-bit read/write registers. TCORA and TCNTV are compared at all times. When the TCORA and TCNTV ...
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Initial Bit Bit Name Value 4 CCLR1 0 3 CCLR0 0 2 CKS2 0 1 CKS1 0 0 CKS0 0 Table 11.2 Clock Signals to Input to TCNTV and Counting Conditions TCRV0 Bit 2 Bit 1 Bit 0 CKS2 CKS1 ...
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Section 11 Timer V 11.3.4 Timer Control/Status Register V (TCSRV) TCSRV indicates the status flag and controls outputs by using a compare match. Initial Bit Bit Name Value 7 CMFB 0 6 CMFA 0 5 OVF ...
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Initial Bit Bit Name Value 1 OS1 0 0 OS0 0 OS3 and OS2 select the output level for compare match B. OS1 and OS0 select the output level for compare match A. The two output levels can be controlled ...
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Section 11 Timer V Initial Bit Bit Name Value ICKS0 0 11.4 Operation 11.4.1 Timer V Operation 1. According to table 11.2, six internal/external clock signals output by prescaler S can be selected as the timer V ...
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Internal clock TCNTV input clock N – 1 TCNTV Figure 11.2 Increment Timing with Internal Clock φ TMCIV (External clock input pin) TCNTV input clock N – 1 TCNTV Figure 11.3 Increment Timing with External Clock φ TCNTV H'FF ...
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Section 11 Timer V φ TCNTV TCORA or TCORB Compare match signal CMFA or CMFB Figure 11.5 CMFA and CMFB Set Timing φ Compare match A signal Timer V output pin φ Compare match A signal TCNTV Figure 11.7 Clear ...
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TMRIV (External counter reset input pin) TCNTV reset signal TCNTV Figure 11.8 Clear Timing by TMRIV Input 11.5 Timer V Application Examples 11.5.1 Pulse Output with Arbitrary Duty Cycle Figure 11.9 shows an example of output of pulses with ...
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Section 11 Timer V 11.5.2 Pulse Output with Arbitrary Pulse Width and Delay from TRGV Input The trigger function can be used to output a pulse with an arbitrary pulse width at an arbitrary delay from the TRGV input, as ...
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Usage Notes The following types of contention or operation can occur in timer V operation. 1. Writing to registers is performed in the T3 state of a TCNTV write cycle TCNTV clear signal is generated in the ...
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Section 11 Timer V Address Internal write signal TCNTV TCORA Compare match signal Figure 11.12 Contention between TCORA Write and Compare Match Clock before switching Clock after switching Count clock TCNTV Figure 11.13 Internal Clock Switching and TCNTV Operation Rev. ...
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The timer W has a 16-bit timer having output compare and input capture functions. The timer W can count external events and output pulses with an arbitrary duty cycle by compare match between the timer counter and four general registers. ...
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Section 12 Timer W Table 12.1 summarizes the timer W functions, and figure 12.1 shows a block diagram of the timer W. Table 12.1 Timer W Functions Item Counter Count clock Internal clocks: , /2, /4, /8 External clock: FTCI ...
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Internal clock: φ /2 Clock φ /4 selector φ /8 External clock: FTCI Comparator [Legend] TMRW: Timer mode register W (8 bits) TCRW: Timer control register W (8 bits) TIERW: Timer interrupt enable register W (8 bits) TSRW: Timer ...
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Section 12 Timer W 12.2 Input/Output Pins Table 12.2 summarizes the timer W pins. Table 12.2 Pin Configuration Name Abbreviation External clock input FTCI Input capture/output FTIOA compare A Input capture/output FTIOB compare B Input capture/output FTIOC compare C Input ...
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Timer Mode Register W (TMRW) TMRW selects the general register functions and the timer output mode. Initial Bit Bit Name Value 7 CTS BUFEB 0 4 BUFEA PWMD 0 1 PWMC ...
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Section 12 Timer W 12.3.2 Timer Control Register W (TCRW) TCRW selects the timer counter clock source, selects a clearing condition, and specifies the timer output levels. Initial Bit Bit Name Value 7 CCLR 0 6 CKS2 0 5 CKS1 ...
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Initial Bit Bit Name Value 0 TOA 0 [Legend] X: Don't care Note: * The change of the setting is immediately reflected in the output value. 12.3.3 Timer Interrupt Enable Register W (TIERW) TIERW controls the timer W interrupt request. ...
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Section 12 Timer W 12.3.4 Timer Status Register W (TSRW) TSRW shows the status of interrupt requests. Initial Bit Bit Name Value 7 OVF All 1 3 IMFD 0 2 IMFC 0 Rev. 3.00 Sep. 14, ...
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Initial Bit Bit Name Value 1 IMFB 0 0 IMFA 0 R/W Description R/W Input Capture/Compare Match Flag B [Setting conditions] TCNT = GRB when GRB functions as an output compare register The TCNT value is transferred to GRB by ...
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Section 12 Timer W 12.3.5 Timer I/O Control Register 0 (TIOR0) TIOR0 selects the functions of GRA and GRB, and specifies the functions of the FTIOA and FTIOB pins. Initial Bit Bit Name Value IOB2 0 5 ...
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Initial Bit Bit Name Value 1 IOA1 0 0 IOA0 0 [Legend] X: Don't care 12.3.6 Timer I/O Control Register 1 (TIOR1) TIOR1 selects the functions of GRC and GRD, and specifies the functions of the FTIOC and FTIOD pins. ...
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Section 12 Timer W Initial Bit Bit Name Value 5 IOD1 0 4 IOD0 IOC2 0 1 IOC1 0 0 IOC0 0 [Legend] X: Don't care Rev. 3.00 Sep. 14, 2006 Page 170 of 408 REJ09B0105-0300 ...