M30262F6GP#U3 Renesas Electronics America, M30262F6GP#U3 Datasheet - Page 86

• Manufacturer Part Number: M30262F6GP#U3
• Description: IC M16C/TINY MCU FLASH 48LQFP
• Manufacturer: Renesas Electronics America
• Series: M16C™ M16C/Tiny/26r

Specifications of M30262F6GP#U3

• Core Processor: M16C/60
• Core Size: 16-Bit
• Speed: 20MHz
• Connectivity: I²C, IEBus, SIO, UART/USART
• Peripherals: DMA, WDT
• Number Of I /o: 38
• Program Memory Size: 48KB (48K x 8)
• Program Memory Type: FLASH
• Ram Size: 2K x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 5.5 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 48-LQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

DIVU
[ Syntax ]
[ Operation ]
[ Function ]
[ Selectable src ]
[ Flag Change ]
[ Description Example ]
[ Related Instructions ]
Chapter 3
Change
R0L/R0
A0/A0
dsp:8[A0]
dsp:16[A0] dsp:16[A1]
dsp:20[A0] dsp:20[A1]
R2R0
Conditions
DIVU.size
If the size specifier (.size) is (.B)
If the size specifier (.size) is (.W)
Flag
O :
DIVU.B
DIVU.B
DIVU.W
• This instruction divides R2R0 (R0)
• If src is an A0 or A1 when the size specifier (.size) you selected is (.B), operation is performed on the
• If you specify (.B) for the size specifier (.size), the O flag is set when the operation resulted in the
• If you specify (.W) for the size specifier (.size), the O flag is set when the operation resulted in the
remainder in R2 (R0H)
for the size specifier (.size).
8 low-order bits of A0 or A1.
quotient exceeding 8 bits or the divisor is 0. At this time, R0L and R0H are indeterminate.
quotient exceeding 16 bits or the divisor is 0. At this time, R0 and R2 are indeterminate.
U
R0L (quotient), R0H (remainder)
R0 (quotient), R2 (remainder)
The flag is set when the operation resulted in the quotient exceeding 16 bits (.W) or 8 bits (.B) or
the divisor is 0; otherwise cleared.
R0H/R1
A1/A1
dsp:8[A1]
R3R1
I
Functions
src
A0
#4
R0
O
B
src
S
R1L/R2
[A0]
dsp:8[SB]
dsp:16[SB]
abs20
A1A0
*1
DIV,DIVX,MUL,MULU
. Shown in ( )
Z
D
C
R1H/R3
[A1]
dsp:8[FB]
abs16
#IMM
*1
R2R0
DIVide Unsigned
by unsigned src and stores the quotient in R0 (R0L)
Unsigned divide
B , W
*1
R0
are the registers that are operated on when you selected (.B)
src
src
68
;A0’s 8 low-order bits is the divisor.
[ Instruction Code/Number of Cycles ]
3.2 Functions
DIVU
Page= 173
*1
and the