C8051F047-GQR Silicon Laboratories Inc, C8051F047-GQR Datasheet - Page 312

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C8051F047-GQR

Manufacturer Part Number
C8051F047-GQR
Description
IC 8051 MCU 32K FLASH 64TQFP
Manufacturer
Silicon Laboratories Inc
Series
C8051F04xr
Datasheets

Specifications of C8051F047-GQR

Core Processor
8051
Core Size
8-Bit
Speed
25MHz
Connectivity
CAN, EBI/EMI, SMBus (2-Wire/I²C), SPI, UART/USART
Peripherals
Brown-out Detect/Reset, POR, PWM, Temp Sensor, WDT
Number Of I /o
32
Program Memory Size
32KB (32K x 8)
Program Memory Type
FLASH
Ram Size
4.25K x 8
Voltage - Supply (vcc/vdd)
2.7 V ~ 3.6 V
Data Converters
A/D 13x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
64-TQFP, 64-VQFP
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
C8051F047-GQR
Manufacturer:
MAXIM
Quantity:
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Part Number:
C8051F047-GQR
Manufacturer:
Silicon Laboratories Inc
Quantity:
10 000
C8051F040/1/2/3/4/5/6/7
24.2.5. 8-Bit Pulse Width Modulator Mode
Each module can be used independently to generate pulse width modulated (PWM) outputs on its associ-
ated CEXn pin. The frequency of the output is dependent on the timebase for the PCA0 counter/timer. The
duty cycle of the PWM output signal is varied using the module's PCA0CPLn capture/compare register.
When the value in the low byte of the PCA0 counter/timer (PCA0L) is equal to the value in PCA0CPLn, the
output on the CEXn pin will be high. When the count value in PCA0L overflows, the CEXn output will be
low (see Figure 24.8). Also, when the counter/timer low byte (PCA0L) overflows from 0xFF to 0x00,
PCA0CPLn is reloaded automatically with the value stored in the counter/timer's high byte (PCA0H) with-
out software intervention. Setting the ECOMn and PWMn bits in the PCA0CPMn register enables 8-Bit
Pulse Width Modulator mode. The duty cycle for 8-Bit PWM Mode is given by Equation 24.2.
Important Note About Capture/Compare Registers: When writing a 16-bit value to the PCA0 Capture/
Compare registers, the low byte should always be written first. Writing to PCA0CPLn clears the ECOMn bit
to '0'; writing to PCA0CPHn sets ECOMn to '1'.
310
W
M
P
1
6
n
0
PCA0CPMn
O
M
E
C
n
C
A
P
P
n
0 0 0 0
C
A
P
N
n
M
A
T
n
O
G
T
n
W
M
P
n
E
C
C
F
n
0
PCA Timebase
Enable
Figure 24.8. PCA 8-Bit PWM Mode Diagram
Equation 24.2. 8-Bit PWM Duty Cycle
Comparator
PCA0CPHn
PCA0CPLn
PCA0L
8-bit
DutyCycle
Overflow
=
match
Rev. 1.5
-------------------------------------------------- -
256 PCA0CPHn
S
R
SET
CLR
Q
Q
256
CEXn
Crossbar
Port I/O

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