C8051F047-GQR Silicon Laboratories Inc, C8051F047-GQR Datasheet - Page 34

• Manufacturer Part Number: C8051F047-GQR
• Description: IC 8051 MCU 32K FLASH 64TQFP
• Manufacturer: Silicon Laboratories Inc
• Series: C8051F04xr

Specifications of C8051F047-GQR

• Core Processor: 8051
• Core Size: 8-Bit
• Speed: 25MHz
• Connectivity: CAN, EBI/EMI, SMBus (2-Wire/I²C), SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, POR, PWM, Temp Sensor, WDT
• Number Of I /o: 32
• Program Memory Size: 32KB (32K x 8)
• Program Memory Type: FLASH
• Ram Size: 4.25K x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 3.6 V
• Data Converters: A/D 13x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 64-TQFP, 64-VQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

C8051F040/1/2/3/4/5/6/7
1.10. Comparators and DACs
Each C8051F040/1/2/3 MCU has two 12-bit DACs, and all C8051F04x devices have three comparators on
chip. The MCU data and control interface to each comparator and DAC is via the Special Function Regis-
ters. The MCU can place any DAC or comparator in low power shutdown mode.
The comparators have software programmable hysteresis and response time. Each comparator can gen-
erate an interrupt on its rising edge, falling edge, or both; these interrupts are capable of waking up the
MCU from sleep mode. The comparators' output state can also be polled in software. The comparator out-
puts can be programmed to appear on the Port I/O pins via the Crossbar.
The DACs are voltage output mode and include a flexible output scheduling mechanism. This scheduling
mechanism allows DAC output updates to be forced by a software write or a Timer 2, 3, or 4 overflow. The
DAC voltage reference is supplied via the dedicated VREFD input pin on C8051F040/2 devices or via the
internal voltage reference on C8051F041/3 devices. The DACs are especially useful as references for the
comparators or offsets for the differential inputs of the ADC.
34
(C 8051F040/1/2/3 only)
(C 8051F040/1/2/3 only)
(Port I/O )
DAC0
DAC1
CPn+
CPn-
C om parator inputs
Port 2.[7:2]
Figure 1.14. Comparator and DAC Diagram
CPn O utput
+
-
CPn
3 Com parators
VREF
DAC 0
VREF
DAC 1
CRO SSBAR
Rev. 1.5
SFR's
(Data
Cntrl)
and
Interrupt
H andler
C IP-51
and