C8051F042-GQR Silicon Laboratories Inc, C8051F042-GQR Datasheet - Page 98

• Manufacturer Part Number: C8051F042-GQR
• Description: IC 8051 MCU 64K FLASH 100TQFP
• Manufacturer: Silicon Laboratories Inc
• Series: C8051F04xr

Specifications of C8051F042-GQR

• Core Processor: 8051
• Core Size: 8-Bit
• Speed: 25MHz
• Connectivity: CAN, EBI/EMI, SMBus (2-Wire/I²C), SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, POR, PWM, Temp Sensor, WDT
• Number Of I /o: 64
• Program Memory Size: 64KB (64K x 8)
• Program Memory Type: FLASH
• Ram Size: 4.25K x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 3.6 V
• Data Converters: A/D 8x8b, 13x10b; D/A 2x10b, 2x12b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 100-TQFP, 100-VQFP
• For Use With: 336-1205 - DEV KIT FOR F040/F041/F042/F043
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

C8051F040/1/2/3/4/5/6/7
98
Bit7:
Bit6:
Bit5:
Bit4:
Bits3-1:
Bit0:
An important note about external convert start (CNVSTR0 and CNVSTR2): If CNVSTR2 is enabled in
AD2EN
R/W
Bit7
AD2EN: ADC2 Enable Bit.
0: ADC2 Disabled. ADC2 is in low-power shutdown.
1: ADC2 Enabled. ADC2 is active and ready for data conversions.
AD2TM: ADC2 Track Mode Bit.
0: Normal Track Mode: When ADC2 is enabled, tracking is continuous unless a conversion is in
process.
1: Low-power Track Mode: Tracking defined by AD2CM2-0 bits (see below).
AD2INT: ADC2 Conversion Complete Interrupt Flag.
This flag must be cleared by software.
0: ADC2 has not completed a data conversion since the last time this flag was cleared.
1: ADC2 has completed a data conversion.
AD2BUSY: ADC2 Busy Bit.
Read:
0: ADC2 Conversion is complete or a conversion is not currently in progress. AD2INT is set to
logic 1 on the falling edge of AD2BUSY.
1: ADC2 Conversion is in progress.
Write:
0: No Effect.
1: Initiates ADC2 Conversion if AD2CM2-0 = 000b
AD2CM2-0: ADC2 Start of Conversion Mode Select.
AD2TM = 0:
000: ADC2 conversion initiated on every write of ‘1’ to AD2BUSY.
001: ADC2 conversion initiated on overflow of Timer 3.
010: ADC2 conversion initiated on rising edge of external CNVSTR2 or CNVSTR0.
011: ADC2 conversion initiated on overflow of Timer 2.
1xx: ADC2 conversion initiated on write of ‘1’ to AD0BUSY (synchronized with ADC0 software-
commanded conversions).
AD2TM = 1:
000: Tracking initiated on write of ‘1’ to AD2BUSY and lasts 3 SAR2 clocks, followed by conver-
sion.
001: Tracking initiated on overflow of Timer 3 and lasts 3 SAR2 clocks, followed by conversion.
010: ADC2 tracks only when CNVSTR2 (or CNVSTR0, See Section 7.2.1) input is logic low; con-
version starts on rising CNVSTR2 edge.
011: Tracking initiated on overflow of Timer 2 and lasts 3 SAR2 clocks, followed by conversion.
1xx: Tracking initiated on write of ‘1’ to AD0BUSY and lasts 3 SAR2 clocks, followed by conver-
sion.
AD2WINT: ADC2 Window Compare Interrupt Flag.
0: ADC2 window comparison data match has not occurred since this flag was last cleared.
1: ADC2 window comparison data match has occurred. This flag must be cleared in software.
the digital crossbar (
on page 204
CNVSTR0 is enabled in the digital crossbar and CNVSTR2 is not enabled, then CNVSTR0 may
serve as the start of conversion for both ADC0 and ADC2.
AD2TM
R/W
Bit6
SFR Definition 7.4. ADC2CN: ADC2 Control
AD2INT AD2BUSY AD2CM2 AD2CM1
), CNVSTR2 will be the external convert start signal for ADC2. However, if only
R/W
Bit5
Section “17.1. Ports 0 through 3 and the Priority Crossbar Decoder”
R/W
Bit4
Rev. 1.5
R/W
Bit3
R/W
Bit2
AD2CM0
R/W
Bit1
SFR Address:
AD2WINT 00000000
SFR Page:
R/W
Bit0
0xE8
2
Reset Value