M30281F6HP#U3B Renesas Electronics America, M30281F6HP#U3B Datasheet - Page 219

• Manufacturer Part Number: M30281F6HP#U3B
• Description: IC M16C/28 MCU FLASH 48K 64LQFP
• Manufacturer: Renesas Electronics America
• Series: M16C™ M16C/Tiny/28r

Specifications of M30281F6HP#U3B

• Core Processor: M16C/60
• Core Size: 16-Bit
• Speed: 20MHz
• Connectivity: I²C, IEBus, SIO, UART/USART
• Peripherals: DMA, POR, PWM, Voltage Detect, WDT
• Number Of I /o: 55
• Program Memory Size: 48KB (48K x 8)
• Program Memory Type: FLASH
• Ram Size: 4K x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 5.5 V
• Data Converters: A/D 13x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 64-LQFP
• For Use With: R0K330290S000BE - KIT EVAL STARTER FOR M16C/29M30290T2-CPE - EMULATOR COMPACT M16C/26A/28/29M30290T2-CPE-HP - EMULATOR COMPACT FOR M16C/TINY
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

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Figure 14.24 Detection of Start and Stop Condition
0
C
2
9
2 /
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14.1.3.1 Detection of Start and Stop Condition
14.1.3.2 Output of Start and Stop Condition
8
0
0
0
Whether a start or a stop condition has been detected is determined.
A start condition-detected interrupt request is generated when the SDA
to low while the SCL
when the SDA
Because the start and stop condition-detected interrupts share the interrupt control register and vec-
tor, check the U2SMR register’s BBS bit to determine which interrupt source is requesting the inter-
rupt.
A start condition is generated by setting the STAREQ bit in the U2SMR4 register to “1” (start).
A restart condition is generated by setting the RSTAREQ bit in the U2SMR4 register to “1” (start).
A stop condition is generated by setting the STPREQ bit in the U2SMR4 register to “1” (start).
The output procedure is described below.
(1) Set the STAREQ bit, RSTAREQ bit or STPREQ bit to “1” (start).
(2) Set the STSPSEL bit in the U2SMR4 register to “1” (output).
Make sure that no interrupts or DMA transfers will occur between (1) and (2).
The function of the STSPSEL bit is shown in Table 14.14 and Figure 14.25.
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4
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7
a
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u
2
p
3
0
, 1
NOTES:
0
(
3 to 6 cycles < setup time
3 to 6 cycles < hold time
M
2
1. When the PCLK1 bit in the PCLKR register is set to "1", the cycles indicates
1
0
0
6
cycles indicated the f2SIO's generation frequency cycles.
7
C
(
(
the f1SIO's generation frequency cycles; when PCLK1 bit is set to "0", the
Start condition)
Stop condition)
2 /
2
, 8
page 197
pin changes state from low to high while the SCL
SCL2
SDA2
SDA2
M
1
2
6
pin is in the high state. A stop condition-detected interrupt request is generated
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2 /
f o
8
3
) B
8
5
(1)
(1)
Setup time
Hold time
2
pin is in the high state.
2
pin changes state from high
14. Serial I/O