R5F64175DFB#U0 Renesas Electronics America, R5F64175DFB#U0 Datasheet
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R32C/117 Group User's Manual: Hardware R32C/117 Group 32 RENESAS MCU M16C Family All information contained in these materials, including products and product specifications, represents information on the product at the time of publication and is subject to change by Renesas ...
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All information included in this document is current as of the date this document is issued. Such information, however, is subject to change without any prior notice. Before purchasing or using any Renesas Electronics products listed herein, please confirm ...
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General Precautions in the Handling of MPU/MCU Products The following usage notes are applicable to all MPU/MCU products from Renesas. For detailed usage notes on the products covered by this manual, refer to the relevant sections of the manual. If ...
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Purpose and Target User This manual is designed to be read primarily by application developers who have an understanding of this microcomputer (MCU) including its hardware functions and electrical characteristics. The user should have a basic understanding of electric ...
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Numbers and Symbols The following explains the denotations used in this manual for registers, bits, pins and various numbers. (1) Registers, bits, and pins Registers, bits, and pins are indicated by symbols. Each symbol has a register/bit/pin identifier after ...
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Registers The following illustration describes registers used throughout this manual. • • • Register Bit Symbol *1 Blank box: Set this bit according to the ...
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Abbreviations and Acronyms The following acronyms and terms are used throughout this manual. Abbreviation/Acronym ACIA Asynchronous Communication Interface Adapter bps bits per second CRC Cyclic Redundancy Check DMA Direct Memory Access DMAC Direct Memory Access Controller GSM Global System ...
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Overview 1.1 Features........................................................................................................................................... 1 1.1.1 Applications .............................................................................................................................. 1 1.1.2 Performance Overview ............................................................................................................. 2 1.2 Product Information ......................................................................................................................... 6 1.3 Block Diagram ................................................................................................................................. 9 1.4 Pin Assignments ............................................................................................................................ 10 1.5 Pin Definitions and Functions ........................................................................................................ 19 2. Central Processing Unit ...
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Power Management 6.1 Voltage Regulators for Internal Logic............................................................................................. 72 6.1.1 Decoupling Capacitor ............................................................................................................. 73 6.2 Low Voltage Detector..................................................................................................................... 74 6.2.1 Operational State of Low Voltage Detector............................................................................. 77 6.2.2 Low Voltage Detection Interrupt ............................................................................................. 77 6.2.3 An Application of Low ...
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ALE Signal............................................................................................................................ 132 RDY Signal ........................................................................................................................... 133 9.3.7 HOLD Signal......................................................................................................................... 136 9.3.8 9.3.9 BCLK Output ........................................................................................................................ 136 9.4 External Bus Status when Accessing Internal Space .................................................................. 136 9.5 Notes on Bus ............................................................................................................................... 137 9.5.1 Notes on System Designing ................................................................................................. ...
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NMI ....................................................................................................................................... 166 11.14.3 External Interrupt .................................................................................................................. 166 12. Watchdog Timer 13. DMAC 13.1 Transfer Cycle.............................................................................................................................. 178 13.1.1 Effect of Transfer Address and Data Bus Width ................................................................... 178 13.1.2 Effect of Bus Timing.............................................................................................................. 179 Effect of RDY Signal ............................................................................................................. ...
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One-shot Timer Mode............................................................................................................211 16.1.4 Pulse-width Modulation Mode............................................................................................... 213 16.2 Timer B ........................................................................................................................................ 216 16.2.1 Timer Mode........................................................................................................................... 219 16.2.2 Event Counter Mode............................................................................................................. 221 16.2.3 Pulse Period/Pulse-width Measure Mode............................................................................. 223 16.3 Notes on Timers........................................................................................................................... 226 16.3.1 Timer A and Timer B............................................................................................................. ...
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SDA Input ............................................................................................................................. 291 18.3.7 Acknowledge ........................................................................................................................ 291 18.3.8 Initialization of Transmit/Receive Operation ......................................................................... 291 18.4 Special Mode 2 ............................................................................................................................ 292 SSi Input Pin Function ( 6)......................................................................................... 294 18.4.1 18.4.2 Clock Phase Setting ............................................................................................................. 295 18.5 ...
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Intelligent I/O 23.1 Base Timer (for Groups .................................................................................................... 344 23.2 Time Measurement (for Groups 0 and 1)..................................................................................... 350 23.3 Waveform Generation (for Groups ................................................................................... 354 23.3.1 Single-phase Waveform Output Mode (for Groups 0 ...
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CAN0 Mask Invalid Register (C0MKIVLR Register) ............................................................ 421 25.1.7 CAN0 Mailbox (C0MBj Register 31)....................................................................... 422 25.1.8 CAN0 Mailbox Interrupt Enable Register (C0MIER Register) ............................................. 426 25.1.9 CAN0 Message Control ...
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Input Function Select Register..................................................................................................... 496 26.4 Pull-up Control Registers (Registers PUR0 to PUR4) ....................................................... 501 26.5 Port Control Register (PCR Register).......................................................................................... 504 26.6 How To Configure Unused Pins................................................................................................... 505 27. Flash Memory 27.1 Overview...................................................................................................................................... 508 27.2 ...
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Power Control....................................................................................................................... 586 29.4 Notes on Bus ............................................................................................................................... 587 29.4.1 Notes on System Designing ................................................................................................. 587 29.4.2 Notes on Register Settings................................................................................................... 587 29.5 Notes on Interrupts ...................................................................................................................... 588 29.5.1 ISP Setting............................................................................................................................ 588 29.5.2 NMI ....................................................................................................................................... 588 29.5.3 External Interrupt ...
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R32C/117 Group RENESAS MCU 1. Overview 1.1 Features The M16C Family offers a robust platform of 32-/16-bit CISC microcomputers (MCUs) featuring high ROM code efficiency, extensive EMI/EMS noise immunity, ultra-low power consumption, high-speed processing in actual applications, and numerous and ...
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R32C/117 Group 1.1.2 Performance Overview Table 1.1 to Table 1.4 list the performance overview of the R32C/117 Group. Table 1.1 Performance Overview for the 144 pin-Package (1/2) Unit Function CPU Central processing unit Memory Voltage Low voltage Detector detector Clock ...
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R32C/117 Group Table 1.2 Performance Overview for the 144-pin Package (2/2) Unit Function Timer Timer A Timer B Three-phase motor control timer Serial UART0 to UART8 Asynchronous/synchronous serial interface × 9 channels Interface A/D Converter D/A Converter CRC Calculator X-Y ...
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R32C/117 Group Table 1.3 Performance Overview for the 100-pin Package (1/2) Unit Function CPU Central processing unit Memory Voltage Low voltage Detector detector Clock Clock generator External Bus Bus and memory Expansion expansion Interrupts Watchdog Timer DMA DMAC DMAC II ...
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R32C/117 Group Table 1.4 Performance Overview for the 100-pin Package (2/2) Unit Function Timer Timer A Timer B Three-phase motor control timer Serial UART0 to UART8 Asynchronous/synchronous serial interface × 9 channels Interface A/D Converter D/A Converter CRC Calculator X-Y ...
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R32C/117 Group 1.2 Product Information Table 1.5 and Table 1.6 list the product information and Figure 1.1 shows the details of the part number. Table 1.5 R32C/117 Group Product List for Normal Speed Version (1/2) Part Number Package Code R5F6417BNFB ...
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R32C/117 Group Table 1.6 R32C/117 Group Product List for High Speed Version (2/2) Part Number Package Code R5F6417BHNFB (P) R5F6417BHDFB PLQP0100KB-A R5F6417BHPFB (P) R5F6417AHNFB (P) R5F6417AHDFB PLQP0100KB-A R5F6417AHPFB (P) R5F64175HNFD (P) R5F64175HDFD PLQP0144KA-A R5F64175HPFD (D) R5F64175HNFB (P) R5F64175HDFB PLQP0100KB-A R5F64175HPFB ...
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R32C/117 Group Part Number XXX FD Figure 1.1 Part Numbering REJ09B0533-0110 Rev.1.10 Sep 08, 2010 Package Code FB : PLQP0100KB PLQP0144KA-A ROM Number Omitted in the flash memory version Temperature Code ...
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R32C/117 Group 1.3 Block Diagram Figure 1.2 shows the block diagram for the R32C/117 Group Port P0 Port P1 Port P2 Peripheral functions Timers: Timer A 16 bits × 5 timers Timer B 16 bits × 6 timers ...
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R32C/117 Group 1.4 Pin Assignments Figure 1.3 and Figure 1.4 show the pin assignments (top view) and Table 1.7 to Table 1.13 list the pin characteristics. IIO0_0 / IIO1_0 / D8 / P1_0 109 AN0_7 / D7 / P0_7 110 ...
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R32C/117 Group Table 1.7 Pin Characteristics for the 144-pin Package (1/4) Pin Control Interrupt Port No. Pin Pin 1 P9_6 2 P9_5 3 P9_4 4 P9_3 5 P9_2 6 P9_1 7 P9_0 P14_6 INT8 8 P14_5 INT7 9 NT6 10 ...
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R32C/117 Group Table 1.8 Pin Characteristics for the 144-pin Package (2/4) Pin Control Interrupt Port No. Pin Pin 37 P7_0 38 P6_7 39 VCC 40 P6_6 41 VSS 42 P6_5 43 P6_4 44 P6_3 45 P6_2 46 P6_1 47 P6_0 ...
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R32C/117 Group Table 1.9 Pin Characteristics for the 144-pin Package (3/4) Pin Control Interrupt Port No. Pin Pin 75 P4_2 76 VSS 77 P4_1 78 P4_0 79 P3_7 80 P3_6 81 P3_5 82 P3_4 83 P3_3 84 P3_2 85 P3_1 ...
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R32C/117 Group Table 1.10 Pin Characteristics for the 144-pin Package (4/4) Pin Control Interrupt Port No. Pin Pin 115 P11_3 116 P11_2 117 P11_1 118 P11_0 119 P0_3 120 P0_2 121 P0_1 122 P0_0 123 P15_7 124 P15_6 125 P15_5 ...
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R32C/117 Group IIO0_2 / IIO1_2 / D10 / P1_2 76 IIO0_1 / IIO1_1 / D9 / P1_1 77 IIO0_0 / IIO1_0 / D8 / P1_0 78 AN0_7 / D7 / P0_7 79 AN0_6 / D6 / P0_6 80 AN0_5 / ...
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R32C/117 Group Table 1.11 Pin Characteristics for the 100-pin Package (1/3) Pin Control Interrupt Port No. Pin Pin 1 P9_4 2 P9_3 3 VDC0 4 P9_1 5 VDC1 6 NSD 7 CNVSS 8 XCIN P8_7 9 XCOUT P8_6 RESET 10 ...
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R32C/117 Group Table 1.12 Pin Characteristics for the 100-pin Package (2/3) Pin Control Interrupt Port No. Pin Pin 39 P5_5 40 P5_4 41 P5_3 42 P5_2 43 P5_1 44 P5_0 45 P4_7 46 P4_6 47 P4_5 48 P4_4 49 P4_3 ...
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R32C/117 Group Table 1.13 Pin Characteristics for the 100-pin Package (3/3) Pin Control Interrupt Port No. Pin Pin 76 P1_2 77 P1_1 78 P1_0 79 P0_7 80 P0_6 81 P0_5 82 P0_4 83 P0_3 84 P0_2 85 P0_1 86 P0_0 ...
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R32C/117 Group 1.5 Pin Definitions and Functions Table 1.14 to Table 1.18 list the pin definitions and functions. Table 1.14 Pin Definitions and Functions (1/4) Function Symbol Power supply VCC, VSS Connecting pins VDC0, VDC1 for decoupling capacitor Analog power ...
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R32C/117 Group Table 1.15 Pin Definitions and Functions (2/4) Function Symbol BC0 /D0, BC2 Bus control pins (1) CS0 to CS3 WR0 / WR1 / WR2 / WR3 , WR / BC0 / BC1 / BC2 / BC3 , RD ...
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R32C/117 Group Table 1.16 Pin Definitions and Functions (3/4) Function Symbol (1, 2) P0_0 to P0_7, I/O port P1_0 to P1_7, P2_0 to P2_7, P3_0 to P3_7, P4_0 to P4_7, P5_0 to P5_7, P6_0 to P6_7, P7_0 to P7_7, P8_0 ...
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R32C/117 Group Table 1.17 Pin Definitions and Functions (4/4) Function Symbol A/D converter AN_0 to AN_7, AN0_0 to AN0_7, AN2_0 to AN2_7, AN15_0 to (1) AN15_7 ADTRG ANEX0 ANEX1 D/A converter DA0, DA1 Reference voltage VREF input Intelligent I/O IIO0_0 ...
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R32C/117 Group Table 1.18 Pin Specifications Pin Names 144- P0_0 to P0_7 P1_0 to P1_7 P2_0 to P2_7 P3_0 to P3_7 P4_0 to P4_7 P5_0 to P5_3 P5_4 to P5_7 P6_0 to P6_7 P7_0 to P7_7 P8_0 to P8_3 P8_4, ...
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R32C/117 Group 2. Central Processing Unit (CPU) The CPU contains registers as shown below. There are two register banks each consisting of registers R2R0, R3R1, R6R4, R7R5 A3, SB, and FB. General purpose b31 registers R2R0 R3R1 R6R4 ...
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R32C/117 Group 2.1 General Purpose Registers 2.1.1 Data Registers (R2R0, R3R1, R6R4, and R7R5) These 32-bit registers are primarily used for transfers and arithmetic/logic operations. Each of the registers can be divided into upper and lower 16-bit registers, e.g. R2R0 ...
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R32C/117 Group 2.1.8.5 Register Bank Select Flag (B flag) This flag selects a register bank. It indicates 0 when the register bank 0 is selected, and 1 when the register bank 1 is selected. 2.1.8.6 Overflow Flag (O flag) This ...
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R32C/117 Group 2.2 Fast Interrupt Registers The following three registers are provided to minimize the overhead of interrupt sequence. Refer to 11.4 “Fast Interrupt” for details. 2.2.1 Save Flag Register (SVF) This 32-bit register is used to save the flag ...
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R32C/117 Group 3. Memory Figure 3.1 shows the memory map of the R32C/117 Group. The R32C/117 Group provides a 4-Gbyte address space from 00000000h to FFFFFFFFh. The internal ROM is mapped to the end of the memory map with the ...
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R32C/117 Group 4. Special Function Registers (SFRs) SFRs are memory-mapped peripheral registers that control the operation of peripherals. Table 4.1 SFR List (1) to Table 4.39 SFR List (39) list the SFR details. Table 4.1 SFR List (1) Address 000000h ...
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R32C/117 Group Table 4.2 SFR List (2) Address 000060h 000061h Timer B5 Interrupt Control Register 000062h UART5 Transmit/NACK Interrupt Control Register 000063h UART2 Receive/ACK Interrupt Control Register/I Interrupt Control Register 000064h UART6 Transmit/NACK Interrupt Control Register 000065h UART3 Receive/ACK Interrupt ...
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R32C/117 Group Table 4.3 SFR List (3) Address 000088h DMA1 Transfer Complete Interrupt Control Register 000089h UART1/4 Bus Collision, Start Condition/Stop Condition Detection Interrupt Control Register 00008Ah DMA3 Transfer Complete Interrupt Control Register 00008Bh Key Input Interrupt Control Register 00008Ch ...
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R32C/117 Group Table 4.4 SFR List (4) Address 0000B0h Intelligent I/O Interrupt Enable Register 0 0000B1h Intelligent I/O Interrupt Enable Register 1 0000B2h Intelligent I/O Interrupt Enable Register 2 0000B3h Intelligent I/O Interrupt Enable Register 3 0000B4h Intelligent I/O Interrupt ...
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R32C/117 Group Table 4.5 SFR List (5) Address 0000E0h 0000E1h CAN0 Receive Interrupt Control Register 0000E2h 0000E3h 0000E4h 0000E5h 0000E6h 0000E7h 0000E8h 0000E9h 0000EAh 0000EBh 0000ECh 0000EDh 0000EEh 0000EFh 0000F0h CAN0 Receive FIFO Interrupt Control Register 0000F1h 0000F2h 0000F3h 0000F4h ...
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R32C/117 Group Table 4.6 SFR List (6) Address 000108h Group 1 Time Measurement/Waveform Generation Register 4 000109h 00010Ah Group 1 Time Measurement/Waveform Generation Register 5 00010Bh 00010Ch Group 1 Time Measurement/Waveform Generation Register 6 00010Dh 00010Eh Group 1 Time Measurement/Waveform ...
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R32C/117 Group Table 4.7 SFR List (7) Address 000140h Group 2 Waveform Generation Register 0 000141h 000142h Group 2 Waveform Generation Register 1 000143h 000144h Group 2 Waveform Generation Register 2 000145h 000146h Group 2 Waveform Generation Register 3 000147h ...
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R32C/117 Group Table 4.8 SFR List (8) Address 000170h Group 2 IEBus Address Register 000171h 000172h Group 2 IEBus Control Register 000173h Group 2 IEBus Transmit Interrupt Source Detect Register 000174h Group 2 IEBus Receive Interrupt Source Detect Register 000175h ...
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R32C/117 Group Table 4.9 SFR List (9) Address 0001A0h Group 0 Base Timer Register 0001A1h 0001A2h Group 0 Base Timer Control Register 0 0001A3h Group 0 Base Timer Control Register 1 0001A4h Group 0 Time Measurement Prescaler Register 6 0001A5h ...
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R32C/117 Group Table 4.10 SFR List (10) Address 0001D0h 0001D1h 0001D2h 0001D3h 0001D4h UART6 Special Mode Register 4 0001D5h UART6 Special Mode Register 3 0001D6h UART6 Special Mode Register 2 0001D7h UART6 Special Mode Register 0001D8h UART6 Transmit/Receive Mode Register ...
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R32C/117 Group Table 4.11 SFR List (11) Address 000200h to 0002BFh 0002C0h X0 Register/Y0 Register 0002C1h 0002C2h X1 Register/Y1 Register 0002C3h 0002C4h X2 Register/Y2 Register 0002C5h 0002C6h X3 Register/Y3 Register 0002C7h 0002C8h X4 Register/Y4 Register 0002C9h 0002CAh X5 Register/Y5 Register ...
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R32C/117 Group Table 4.12 SFR List (12) Address 0002F0h 0002F1h 0002F2h 0002F3h 0002F4h UART4 Special Mode Register 4 0002F5h UART4 Special Mode Register 3 0002F6h UART4 Special Mode Register 2 0002F7h UART4 Special Mode Register 0002F8h UART4 Transmit/Receive Mode Register ...
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R32C/117 Group Table 4.13 SFR List (13) Address 000320h 000321h 000322h 000323h 000324h UART3 Special Mode Register 4 000325h UART3 Special Mode Register 3 000326h UART3 Special Mode Register 2 000327h UART3 Special Mode Register 000328h UART3 Transmit/Receive Mode Register ...
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R32C/117 Group Table 4.14 SFR List (14) Address 000350h Timer B0 Register 000351h 000352h Timer B1 Register 000353h 000354h Timer B2 Register 000355h 000356h Timer A0 Mode Register 000357h Timer A1 Mode Register 000358h Timer A2 Mode Register 000359h Timer ...
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R32C/117 Group Table 4.15 SFR List (15) Address 000380h A/D0 Register 0 000381h 000382h A/D0 Register 1 000383h 000384h A/D0 Register 2 000385h 000386h A/D0 Register 3 000387h 000388h A/D0 Register 4 000389h 00038Ah A/D0 Register 5 00038Bh 00038Ch A/D0 ...
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R32C/117 Group Table 4.16 SFR List (16) Address 0003B0h 0003B1h 0003B2h 0003B3h 0003B4h 0003B5h 0003B6h 0003B7h 0003B8h 0003B9h 0003BAh 0003BBh 0003BCh 0003BDh 0003BEh 0003BFh 0003C0h Port P0 Register 0003C1h Port P1 Register 0003C2h Port P0 Direction Register 0003C3h Port P1 ...
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R32C/117 Group Table 4.17 SFR List (17) Address 0003E0h 0003E1h 0003E2h 0003E3h 0003E4h 0003E5h 0003E6h 0003E7h 0003E8h 0003E9h 0003EAh 0003EBh 0003ECh 0003EDh 0003EEh 0003EFh 0003F0h Pull-up Control Register 0 0003F1h Pull-up Control Register 1 0003F2h Pull-up Control Register 2 0003F3h ...
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R32C/117 Group Table 4.18 SFR List (18) Address 040000h Flash Memory Control Register 0 040001h Flash Memory Status Register 0 040002h 040003h 040004h 040005h 040006h 040007h 040008h Flash Register Protection Unlock Register 0 040009h Flash Memory Control Register 1 04000Ah ...
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R32C/117 Group Table 4.19 SFR List (19) Address 040030h to 04003Fh 040040h 040041h 040042h 040043h 040044h Processor Mode Register 0 040045h 040046h System Clock Control Register 0 040047h System Clock Control Register 1 040048h Processor Mode Register 3 040049h 04004Ah ...
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R32C/117 Group Table 4.20 SFR List (20) Address 040094h 040095h 040096h 040097h Three-phase Output Buffer Control Register 040098h Input Function Select Register 0 040099h Input Function Select Register 1 04009Ah Input Function Select Register 2 04009Bh Input Function Select Register ...
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R32C/117 Group Table 4.21 SFR List (21) Address 0400C0h Port P4_0 Function Select Register 0400C1h Port P5_0 Function Select Register 0400C2h Port P4_1 Function Select Register 0400C3h Port P5_1 Function Select Register 0400C4h Port P4_2 Function Select Register 0400C5h Port ...
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R32C/117 Group Table 4.22 SFR List (22) Address 0400F0h Port P10_0 Function Select Register 0400F1h Port P11_0 Function Select Register 0400F2h Port P10_1 Function Select Register 0400F3h Port P11_1 Function Select Register 0400F4h Port P10_2 Function Select Register 0400F5h Port ...
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R32C/117 Group Table 4.23 SFR List (23) Address 040120h to 04403Fh 044040h 044041h 044042h 044043h 044044h 044045h 044046h 044047h 044048h 044049h 04404Ah 04404Bh 04404Ch 04404Dh 04404Eh Watchdog Timer Start Register 04404Fh Watchdog Timer Control Register 044050h 044051h 044052h 044053h 044054h ...
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R32C/117 Group Table 4.24 SFR List (24) Address 044060h 044061h 044062h 044063h 044064h 044065h 044066h 044067h 044068h 044069h 04406Ah 04406Bh 04406Ch 04406Dh External Interrupt Request Source Select Register 1 04406Eh 04406Fh External Interrupt Request Source Select Register 0 044070h DMA0 ...
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R32C/117 Group Table 4.25 SFR List (25) Address 044090h to 0443FFh 044400h I 2 C-bus Transmit/Receive Shift Register 044401h 044402h I 2 C-bus Slave Address Register 044403h I 2 C-bus Control Register 0 044404h I 2 C-bus Clock Control Register ...
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R32C/117 Group Table 4.26 SFR List (26) Address 046800h to 047BFFh 047C00h CAN0 Mailbox 0: Message Identifier 047C01h 047C02h 047C03h 047C04h 047C05h CAN0 Mailbox 0: Data Length 047C06h CAN0 Mailbox 0: Data Field 047C07h 047C08h 047C09h 047C0Ah 047C0Bh 047C0Ch 047C0Dh ...
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R32C/117 Group Table 4.27 SFR List (27) Address 047C30h CAN0 Mailbox 3: Message Identifier 047C31h 047C32h 047C33h 047C34h 047C35h CAN0 Mailbox 3: Data Length 047C36h CAN0 Mailbox 3: Data Field 047C37h 047C38h 047C39h 047C3Ah 047C3Bh 047C3Ch 047C3Dh 047C3Eh CAN0 Mailbox ...
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R32C/117 Group Table 4.28 SFR List (28) Address 047C60h CAN0 Mailbox 6: Message Identifier 047C61h 047C62h 047C63h 047C64h 047C65h CAN0 Mailbox 6: Data Length 047C66h CAN0 Mailbox 6: Data Field 047C67h 047C68h 047C69h 047C6Ah 047C6Bh 047C6Ch 047C6Dh 047C6Eh CAN0 Mailbox ...
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R32C/117 Group Table 4.29 SFR List (29) Address 047C90h CAN0 Mailbox 9: Message Identifier 047C91h 047C92h 047C93h 047C94h 047C95h CAN0 Mailbox 9: Data Length 047C96h CAN0 Mailbox 9: Data Field 047C97h 047C98h 047C99h 047C9Ah 047C9Bh 047C9Ch 047C9Dh 047C9Eh CAN0 Mailbox ...
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R32C/117 Group Table 4.30 SFR List (30) Address 047CC0h CAN0 Mailbox 12: Message Identifier 047CC1h 047CC2h 047CC3h 047CC4h 047CC5h CAN0 Mailbox 12: Data Length 047CC6h CAN0 Mailbox 12: Data Field 047CC7h 047CC8h 047CC9h 047CCAh 047CCBh 047CCCh 047CCDh 047CCEh CAN0 Mailbox ...
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R32C/117 Group Table 4.31 SFR List (31) Address 047CF0h CAN0 Mailbox 15: Message Identifier 047CF1h 047CF2h 047CF3h 047CF4h 047CF5h CAN0 Mailbox 15: Data Length 047CF6h CAN0 Mailbox 15: Data Field 047CF7h 047CF8h 047CF9h 047CFAh 047CFBh 047CFCh 047CFDh 047CFEh CAN0 Mailbox ...
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R32C/117 Group Table 4.32 SFR List (32) Address 047D20h CAN0 Mailbox 18: Message Identifier 047D21h 047D22h 047D23h 047D24h 047D25h CAN0 Mailbox 18: Data Length 047D26h CAN0 Mailbox 18: Data Field 047D27h 047D28h 047D29h 047D2Ah 047D2Bh 047D2Ch 047D2Dh 047D2Eh CAN0 Mailbox ...
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R32C/117 Group Table 4.33 SFR List (33) Address 047D50h CAN0 Mailbox 21: Message Identifier 047D51h 047D52h 047D53h 047D54h 047D55h CAN0 Mailbox 21: Data Length 047D56h CAN0 Mailbox 21: Data Field 047D57h 047D58h 047D59h 047D5Ah 047D5Bh 047D5Ch 047D5Dh 047D5Eh CAN0 Mailbox ...
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R32C/117 Group Table 4.34 SFR List (34) Address 047D80h CAN0 Mailbox 24: Message Identifier 047D81h 047D82h 047D83h 047D84h 047D85h CAN0 Mailbox 24: Data Length 047D86h CAN0 Mailbox 24: Data Field 047D87h 047D88h 047D89h 047D8Ah 047D8Bh 047D8Ch 047D8Dh 047D8Eh CAN0 Mailbox ...
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R32C/117 Group Table 4.35 SFR List (35) Address 047DB0h CAN0 Mailbox 27: Message Identifier 047DB1h 047DB2h 047DB3h 047DB4h 047DB5h CAN0 Mailbox 27: Data Length 047DB6h CAN0 Mailbox 27: Data Field 047DB7h 047DB8h 047DB9h 047DBAh 047DBBh 047DBCh 047DBDh 047DBEh CAN0 Mailbox ...
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R32C/117 Group Table 4.36 SFR List (36) Address 047DE0h CAN0 Mailbox 30: Message Identifier 047DE1h 047DE2h 047DE3h 047DE4h 047DE5h CAN0 Mailbox 30: Data Length 047DE6h CAN0 Mailbox 30: Data Field 047DE7h 047DE8h 047DE9h 047DEAh 047DEBh 047DECh 047DEDh 047DEEh CAN0 Mailbox ...
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R32C/117 Group Table 4.37 SFR List (37) Address 047E10h CAN0 Acceptance Mask Register 4 047E11h 047E12h 047E13h 047E14h CAN0 Acceptance Mask Register 5 047E15h 047E16h 047E17h 047E18h CAN0 Acceptance Mask Register 6 047E19h 047E1Ah 047E1Bh 047E1Ch CAN0 Acceptance Mask Register ...
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R32C/117 Group Table 4.38 SFR List (38) Address 047F20h CAN0 Message Control Register 0 047F21h CAN0 Message Control Register 1 047F22h CAN0 Message Control Register 2 047F23h CAN0 Message Control Register 3 047F24h CAN0 Message Control Register 4 047F25h CAN0 ...
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R32C/117 Group Table 4.39 SFR List (39) Address 047F40h CAN0 Control Register 047F41h 047F42h CAN0 Status Register 047F43h 047F44h CAN0 Bit Configuration Register 047F45h 047F46h 047F47h CAN0 Clock Select Register 047F48h CAN0 Receive FIFO Control Register 047F49h CAN0 Receive FIFO ...
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R32C/117 Group 5. Resets Three types of reset operations can be used to reset the MCU: hardware reset, software reset, and watchdog timer reset. 5.1 Hardware Reset A hardware reset is generated when a low signal is applied to the ...
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R32C/117 Group XIN 20 or more cycles are required RESET Microprocessor mode BCLK 8-bit bus Address RD 16-bit bus Address RD 32-bit bus Address RD Single-chip mode (1) Address Note: 1. Address data is not output from pins in single-chip ...
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R32C/117 Group Pin States while RESET Pin is Held Low Table 5.1 Pin Name CNVSS = VSS P0 Input port (high-impedance) P1 Input port (high-impedance) P2, P3 Input port (high-impedance) P4_0 to P4_6 Input port (high-impedance) P4_7 Input port (high-impedance) ...
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R32C/117 Group 5.2 Software Reset A software reset is generated when the PM03 bit in the PM0 register is set to 1 (MCU is reset). When a software reset is released, the CPU, SFRs, and pins are initialized. Then, the ...
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R32C/117 Group 6. Power Management 6.1 Voltage Regulators for Internal Logic The supply voltage for internal logic is generated by reducing the input voltage from the VCC pin with the voltage regulators. Figure 6.1 shows a block diagram of the ...
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R32C/117 Group 6.1.1 Decoupling Capacitor An external decoupling capacitor is required to stabilize internal voltage. The capacitor should be beneficially effective at higher frequencies and maintain more stable capacitance irrespective of temperature change. In general, ceramic capacitors are recommended. The ...
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R32C/117 Group 6.2 Low Voltage Detector The low voltage detector monitors the supply voltage of VCC pin. This circuit is used to monitor the power supply upstream of the voltage regulators for internal logic and provide advanced warning that the ...
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R32C/117 Group Low Voltage Detector Control Register Symbol LVDC Bit Symbol VDEN LVDIEN (b7-b4) Notes: 1. Set the PRC31 bit in the PRCR3 register to 1 (write enabled) before rewriting this register. ...
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R32C/117 Group Detection Voltage Configuration Register Symbol 0 1 DVCR Bit Symbol (b6-b4) Notes: 1. Set the PRC31 bit in the PRCR3 register to 1 (write enabled) before rewriting this register. The ...
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R32C/117 Group 6.2.1 Operational State of Low Voltage Detector The low voltage detector starts running after td(E-A) if the VDEN bit in the LVDC register is set to 1 (low voltage detection enabled). When the input voltage to the VCC ...
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R32C/117 Group 6.2.3 An Application of Low Voltage Detector Figure 6.7 shows an application of the low voltage detection interrupt. The supply voltage for internal logic is generated by reducing the input voltage from the VCC pin with the voltage ...
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R32C/117 Group 7. Processor Mode 7.1 Types of Processor Modes The R32C/100 Series supports three types of processor modes: single-chip mode, memory expansion mode, and microprocessor mode. Table 7.1 lists the characteristics of each processor mode. Table 7.1 Processor Mode ...
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R32C/117 Group Processor Mode Register Symbol PM0 Bit Symbol Notes: 1. This register should be rewritten after the PRC1 bit in the PRCR register is set to 1 ...
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R32C/117 Group Single-chip Mode SFRs Internal RAM Reserved (internal RAM SFRs 2 0 ...
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R32C/117 Group 8. Clock Generator 8.1 Clock Generator Types Four circuits are included to generate a system clock signal: • Main clock oscillator • Sub clock oscillator • PLL frequency synthesizer • On-chip oscillator Table 8.1 lists specifications of clock ...
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R32C/117 Group WAIT instruction (Wait mode) STOP instruction (Stop mode) RESET NMI Low voltage detection interrupt Output signal from priority resolver Main clock oscillator XIN XOUT CM05 CM10 CM02 wait_mode stop_mode Sub clock oscillator XCIN XCOUT CM04 stop_mode On-chip oscillator ...
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R32C/117 Group Clock Control Register Symbol 0 CCR Bit Symbol CCD0 CCD1 Notes: 1. Set the PRR register to AAh (write enabled) before rewriting this register. 2. The divide ratios of the ...
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R32C/117 Group System Clock Control Register Symbol 0 CM0 Bit Symbol Notes: 1. Set the PRC0 bit in the PRCR register to 1 (write enabled) before rewriting this register. 2. When ...
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R32C/117 Group System Clock Control Register Symbol CM1 Bit Symbol (b4-b1) Notes: 1. Set the PRC0 bit in the PRCR register to 1 (write enabled) before ...
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R32C/117 Group Oscillator Stop Detection Register Symbol CM2 Bit Symbol (b7-b4) Notes: 1. Set the PRC0 bit in the PRCR register to 1 (write enabled) before rewriting ...
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R32C/117 Group Count Source Prescaler Register Symbol TCSPR Bit Symbol (b6-b4) Note: 1. The CST bit should be set rewrite bits CNT3 to CNT0. Figure 8.7 ...
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R32C/117 Group Processor Mode Register Symbol PM2 Bit Symbol (b3-b2) Notes: 1. Set the PRC1 bit in the PRCR register to 1 (write enabled) before rewriting ...
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R32C/117 Group Processor Mode Register Symbol PM3 Bit Symbol (b4-b0) Notes: 1. Set the PRC0 bit in the PRCR register to 1 (write enabled) before ...
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R32C/117 Group The following sections illustrate clocks generated in clock generators. 8.1.1 Main Clock The main clock is generated by the main clock oscillator. This clock can be a clock source for the PLL reference clock or the peripheral clock. ...
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R32C/117 Group 8.1.2 Sub Clock (fC) The sub clock is generated by the sub clock oscillator. This clock can be a clock source for the CPU clock and a count source for timers A and output from ...
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R32C/117 Group 8.1.3 PLL Clock The PLL clock is generated by the PLL frequency synthesizer based on the main clock. This clock can be a clock source for any clock including the CPU clock and the peripheral clock. Figure 8.13 ...
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R32C/117 Group PLL Control Register Symbol PLC1 Bit Symbol (b7-b5) Note: 1. Set the PRC2 bit in the PRCR register to 1 (write enabled) just before rewriting this ...
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R32C/117 Group Table 8.2 PLC1 and PLC0 Register Settings Reference Main Clock r Clock 4 MHz 2 2 MHz 6 MHz 2 3 MHz 8 MHz 3 2.6667 MHz 10 MHz 5 2 MHz 12 MHz 4 3 MHz 16 ...
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R32C/117 Group 8.1.4 On-chip Oscillator Clock The on-chip oscillator clock is generated by the on-chip oscillator (OCO). This clock can be a clock source for the CPU clock and for a count source of timers A and B. This clock ...
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R32C/117 Group 8.2 Oscillator Stop Detection This function is to detect the main clock is stopped when its oscillator stops running by external source. When the CM20 bit in the CM2 register is set to 1 (oscillator stop detection enabled), ...
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R32C/117 Group 8.4 CPU Clock and Peripheral Bus Clock The CPU operating clock is referred to as the CPU clock. The CPU clock after a reset is the base clock divided by 2. The CPU clock source is the base ...
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R32C/117 Group 8.6 Clock Output Function Low speed clocks, f8, and f32 are available to be output from the CLKOUT pin. In memory expansion mode or microprocessor mode, the BCLK, that is, the peripheral bus clock which is the base ...
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R32C/117 Group 8.7 Power Control Power control contains three modes: wait mode, stop mode, and normal operating mode. The name “normal operating mode” is used restrictively in this chapter, and it indicates all other modes except wait mode and stop ...
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R32C/117 Group 8.7.1 Normal Operating Mode Normal operating mode is classified into the five modes shown below. In normal operating mode, the CPU clock and peripheral clock are provided to operate the CPU and peripheral functions. Power consumption is controlled ...
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R32C/117 Group The state transition within normal operating mode can be very complicated; therefore only the block diagrams of typical state transitions are shown. Figure 8.17 to Figure 8.19 show block diagrams of the respective state transition: state when the ...
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R32C/117 Group PLL self-oscillation mode (after reset) Main clock oscillation Sub clock stop CM04 = 1 PLL clock oscillation (self-oscillation) CPU clock: f(PLL PLC0 = 01h PLC1 = 1Fh CCR = 00011000b CM04 = 0 CM04 = 0 ...
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R32C/117 Group PLL self-oscillation mode (after reset) Main clock oscillation PLL clock oscillation (self-oscillation) CM30 = 1 CPU clock: f(PLL PLC0 = 01h PLC1 = 1Fh CCR = 00011000b CM05 = 0 CM10 = 0 CM30 = 0 ...
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R32C/117 Group PLL self-oscillation mode (after reset) Main clock oscillation On-chip oscillator clock stop CM31 = 1 PLL clock oscillation (self-oscillation) CPU clock: f(PLL PLC0 = 01h PLC1 = 1Fh CCR = 00011000b CM31 = 0 CM05 = ...
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R32C/117 Group 8.7.2 Wait Mode In wait mode, due to the base clock stop, the CPU clock and peripheral bus clock stop running as well. The CPU and watchdog timer, operated by the CPU clock, also stop. Since the main ...
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R32C/117 Group 8.7.2.3 Pin State in Wait Mode Table 8.5 lists pin state in wait mode. Table 8.5 Pin State in Wait Mode Pin Address bus, Data bus, CS0 to CS3 , BC0 to BC3 WR0 ...
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R32C/117 Group Table 8.6 Interrupts to Exit Wait Mode and Usage Conditions Interrupt NMI (1) External interrupt Key input interrupt Low voltage detection interrupt Available Timer A interrupt Timer B interrupt (2) Serial interface interrupt A/D conversion interrupt Intelligent I/O ...
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R32C/117 Group 8.7.3 Stop Mode In stop mode, all of the clocks, except for those that are protected, stop running. That is, the CPU and peripheral functions, operated by the CPU clock and peripheral clock, also stop. This is the ...
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R32C/117 Group 8.7.3.2 Pin State in Stop Mode Table 8.7 lists pin state in stop mode. Table 8.7 Pin State in Stop Mode Pin Address bus, Data bus, CS0 to CS3 , BC0 to BC3 WR0 ...
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R32C/117 Group 8.8 System Clock Protection The system clock protection is a function to disable clock change when the PLL clock is selected as base clock source. This prevents the CPU clock, which is out of control, from stopping. When ...
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R32C/117 Group 8.9 Notes on Clock Generator 8.9.1 Sub Clock 8.9.1.1 Oscillation Parameter Matching The constant matching of sub clock oscillator should be evaluated in both cases when the drive power is high and low. Contact your oscillator manufacturer for ...
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R32C/117 Group 9. Bus This MCU provides internal bus and external bus. The internal bus contains fast bus (CPU bus) and slow bus (peripheral bus). Figure 9.1 shows a block diagram of the bus. ROM CPU data bus (64-bit) CPU ...
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R32C/117 Group 9.2 Peripheral Bus Timing Setting The peripheral bus of 16-/32-bit width operates at a frequency MHz (the theoretical value and the maximum frequency of each product group are as defined by f(BCLK) in 28. “Electrical ...
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R32C/117 Group 9.3 External Bus Setting External bus of 8-/16-/32-bit width operates at a frequency MHz (the theoretical value and the maximum frequency of each product group are as defined by f(BCLK) in 28. “Electrical Characteristics”). The ...
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R32C/117 Group Pattern 1. Address bus: changed, Chip select signal: changed, at the first cycle after accessing an external space When a CSy space is accessed in the first cycle after the access to a CSx space, both the address ...
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R32C/117 Group Chip Select Output Pin Setting Register Symbol CSOP0 Bit Symbol (b3-b0) P4_4B P4_5B P4_6B P4_7B Notes: 1. Set the PRC1 bit in the PRCR register to 1 (write enabled) ...
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R32C/117 Group Chip Select Output Pin Setting Register Symbol CSOP2 Bit Symbol P11_0B P11_1B P11_2B P11_3B (b7-b4) Notes: 1. Set the PRC1 bit in the PRCR register to 1 (write enabled) ...
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R32C/117 Group Chip Selects 1 and 2 Boundary Setting Register b7 b0 Symbol CB12 Set this register to the value from A25 to A18 of the start address of CS1 space. The immediately preceding address mentioned above and lower is ...
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R32C/117 Group Address 00000000h Internal space 00080000h CS3 space (1) CB23 CS2 space (1) CB12 CS1 space (1) CB01 02000000h Unavailable FE000000h CS0 space (1) FFE00000h Internal space FFFFFFFFh Note: 1. Each CS space is available ...
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R32C/117 Group Address 00000000h Internal space 00080000h CS3 space (1) CB23 CS2 space (1) CB12 CS1 space (1) CB01 02000000h Unavailable FE000000h CS0 space (1) FFFFFFFFh Note: 1. Each CS space is available when the CS ...
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R32C/117 Group External Bus Control Register i b15 Symbol 1 1 EBC0, EBC1 EBC2, EBC3 Bit Symbol ESUR0 ESUR1 ESUW0 ESUW1 Notes: 1. Set the PRR register to AAh (write enabled) before rewriting this register. 2. Refer ...
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R32C/117 Group 9.3.3 Separate Bus/Multiplexed Bus Selection The bus format is selectable between separate bus format and multiplexed bus format. The bus format for each space is set using the MPX bit in registers EBC0 to EBC3. To specify multiplexed ...
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R32C/117 Group Table 9.2 Processor Mode and Pin Functions Process Single- Microprocessor Mode/Memory Expansion Mode or Mode Chip Mode Bus Separate bus only — format (EXMPX = 0) Data bus 8/16 bits — 8 bits only width (mixed) P0_0 to ...
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R32C/117 Group Table 9.3 Bus Format and Pin Functions (in Microprocessor Mode/Memory Expansion Mode) Bus Format MPX bit Bus width 8 bits Bits BW1 to 00b BW0 P0_0 to P0_7 P1_0 to P1_7 I/O ports P2_0 A0 P2_1 A1 P2_2 ...
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R32C/117 Group 9.3.4 Read and Write Signals In 16- or 32-bit data bus, the PM02 bit in the PM0 register selects a combination BC0 , BC1 , BC2 , and BC3 WR0 ...
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R32C/117 Group Signals RD, WR, BC0, BC1, BC2, and BC3 Table 9.5 Data Bus RD WR BC0 Width ( bits ...
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R32C/117 Group 9.3.5 External Bus Timing The external bus timing is set using registers EBC0 to EBC3. The reference clock is the base clock set using bits BCD1 and BCD0 in the CCR register. Table 9.6 lists the bit setting ...
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R32C/117 Group Table 9.8 The Tsu(A-W) and the Bit Settings: MPY1, MPY0, ESUW1, and ESUW0 (unit: cycles) MPY1 and MPY0 Bit Settings ESUW1 and ESUW0 00b Bit Settings mpy = 1 00b suw = 0 1 01b 2 suw = ...
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R32C/117 Group (1) When the EBCi register is XX01 0100 0001 0000b Base clock (internal signal) CS, BC0 to BC3 Address Data RD WR, WR0 to WR3 (2) When the EBCi register is XX01 1001 0001 0101b Base clock (internal ...
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R32C/117 Group (1) When the EBCi register is XX11 0100 0001 0100b Base clock (internal signal) CS, BC0 to BC3 Address / Data ALE RD WR, WR0 to WR3 (2) When the EBCi register is XX11 1010 0001 1010b Base ...
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R32C/117 Group 9.3.6 ALE Signal The ALE signal latches an address of the multiplexed bus. The address should be latched on the falling edge of the ALE signal. This signal is output to internal space or external space. (1) 8-bit ...
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R32C/117 Group RDY Signal 9.3.7 The RDY signal facilitates access to external devices requiring longer access time used when accessing an external device with lower access rate than the timing set in registers EBC0 to EBC3 or when ...
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R32C/117 Group Table 9.10 Setting Conditions of the EBCi register when Using the Circuit in Figure 9. Peripheral Bus Clock Frequency BCLK = 1/2 base clock BCLK = 1/3 base clock BCLK = 1/4 base ...
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R32C/117 Group (1) In separate bus format Base Clock Clock Enable (Internal signal) CS, BC0 to BC3 Address RD Data (Read) WR, WR0 to WR3 Data (Write) RDY (2) In multiplexed bus format Base Clock Clock Enable (Internal signal) CS, ...
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R32C/117 Group HOLD Signal 9.3.8 The HOLD signal is used when the external bus master requests the external bus from the CPU. When the external bus master drives the HOLD pin low, the CPU outputs a low signal from the ...
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R32C/117 Group 9.5 Notes on Bus 9.5.1 Notes on System Designing When the flash memory rewrite is performed in CPU rewrite mode using memory expansion mode, the use of CS0 space and CS3 space has the following restrictions: • If ...
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R32C/117 Group 10. Protection This function protects important registers from being easily overwritten when a program goes out of control. It contains the following registers: PRCR, PRCR2, PRCR3, and PRR. 10.1 Protect Register (PRCR Register) Figure 10.1 shows the PRCR ...
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R32C/117 Group 10.2 Protect Register 2 (PRCR2 Register) Figure 10.2 shows the PRCR2 register which protects the CM3 register only. Protect Register Symbol PRCR2 Bit Symbol (b6-b0) PRC27 Figure 10.2 PRCR2 ...
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R32C/117 Group 10.4 Protect Release Register (PRR Register) Figure 10.4 shows the PRR register. Registers protected by the PRR register are as follows: CCR, FMCR, PBC, FEBC0, FEBC3, EBC0 to EBC3, CB01, CB12, and CB23. To write to the registers ...
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R32C/117 Group 11. Interrupts 11.1 Interrupt Types Figure 11.1 shows types of interrupts. Software (Non-maskable interrupt) Interrupt Hardware Notes: 1.The peripheral functions in the MCU are used to generate the peripheral interrupt. 2.These interrupts are exclusively used for development support ...
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R32C/117 Group 11.2 Software Interrupt Software interrupts are non-maskable. A software interrupt is generated by executing an instruction. There are five types of software interrupts as follows: (1) Undefined Instruction Interrupt This interrupt occurs when the UND instruction is executed. ...
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R32C/117 Group 11.3 Hardware Interrupt There are two kinds of hardware interrupts: special interrupt and peripheral interrupt. In peripheral interrupts, only one interrupt with the highest priority can be specified as a fast interrupt. 11.3.1 Special Interrupt Special interrupts are ...
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R32C/117 Group 11.4 Fast Interrupt Fast interrupt enables the CPU to minimize the overhead of interrupt sequence. In peripheral interrupts, only one interrupt with the highest priority can be specified as the fast interrupt. Steps to set up a fast ...
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R32C/117 Group 11.5.1 Fixed Vector Table The fixed vector table is allocated in addresses FFFFFFDCh to FFFFFFFFh. Table 11.1 lists the fixed vector table. Table 11.1 Fixed Vector Table Vector Table Addresses Interrupt Source (Address (L) to Address (H)) Undefined ...
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R32C/117 Group Table 11.2 Relocatable Vector Table (1/4) Interrupt Source (2) BRK instruction Reserved UART5 transmission, NACK (3) UART5 reception, ACK UART6 transmission, NACK (3) UART6 reception, ACK Bus collision detection, start condition detection, or stop condition detection (3, 4) ...
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R32C/117 Group Table 11.3 Relocatable Vector Table (2/4) Interrupt Source UART2 transmission, NACK (3) bus interface (2) 2 UART2 reception, ACK /I C-bus line (3) UART3 transmission, NACK (2) UART3 reception, ACK UART4 transmission, NACK (2) UART4 reception, ACK Bus ...
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R32C/117 Group Table 11.4 Relocatable Vector Table (3/4) Interrupt Source Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved CAN0 transmit FIFO CAN0 receive FIFO Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved ...
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R32C/117 Group Table 11.5 Relocatable Vector Table (4/4) Interrupt Source CAN0 transmission CAN0 reception CAN0 error Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved ...
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R32C/117 Group 11.6 Interrupt Request Acceptance Software interrupts and special interrupts are accepted whenever their interrupt request is generated. Peripheral interrupts, however, are only accepted if the conditions below are met: • I flag = 1 • IR bit = ...
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R32C/117 Group 11.6.2 Interrupt Control Register The interrupt control registers control each peripheral interrupt. Figure 11.3 and Figure 11.4 show the interrupt control registers. Interrupt Control Register Symbol TA0IC to TA4IC TB0IC ...
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R32C/117 Group Interrupt Control Register Symbol INT0IC to INT2IC INT3IC to INT5IC INT6IC to INT8IC Bit Symbol (b7-b6) Notes: 1. When the 16- or 32-bit data bus is used in microprocessor mode ...
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R32C/117 Group When rewriting the interrupt control register, no corresponding interrupt request should be generated may be generated, disable all the maskable interrupts before the rewrite. When enabling the maskable interrupts immediately after the rewrite, there should be ...
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R32C/117 Group 11.6.3 Wake-up IPL Setting Register The wake-up IPL setting register (registers RIPL1 and RIPL2) is used for an interrupt to exit wait or stop mode, or for the fast interrupt. Refer to 8.7.2 “Wait Mode”, 8.7.3 “Stop Mode”, ...
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R32C/117 Group 11.6.4 Interrupt Sequence The interrupt sequence is performed from when an interrupt request has been accepted until the interrupt handler starts. For most instructions, when an interrupt request is generated while an instruction is being executed, the requested ...
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R32C/117 Group 11.6.5 Interrupt Response Time The interrupt response time, as shown in Figure 11.6, consists of two non-overlapping time segments: (a) the period from when an interrupt request is generated until the instruction being executed is completed; and (b) ...
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R32C/117 Group 11.6.6 IPL After Interrupt Request Acceptance When a peripheral interrupt request is accepted, the interrupt request level is set in the IPL (processor interrupt priority level). Software interrupts and special interrupts have no interrupt request level. For these ...
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R32C/117 Group 11.7 Register Restoring from Interrupt Handler When the REIT instruction is executed at the end of the interrupt handler, the saved values of the flag register (FLG) and the program counter (PC) are restored from the stack, and ...
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R32C/117 Group Request level of interrupts High UART5 transmission UART5 reception UART6 transmission UART6 reception Bus collision (UART5, 6) DMA0 DMA1 DMA2 DMA3 Timer A0 Timer A1 Timer A2 Timer A3 Timer A4 UART0 transmission UART0 reception UART1 transmission UART1 ...
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R32C/117 Group 11.10 External Interrupt An external interrupt is generated by an external input applied to the INTi pin ( 8). The LVS bit in the INTiIC register selects whether an interrupt is triggered by the effective ...
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R32C/117 Group External Interrupt Request Source Select Register Symbol IFSR1 Bit Symbol IFSR10 IFSR11 IFSR12 (b5-b3) IFSR16 Note: 1. This bit should be set select the level sensitive ...
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R32C/117 Group 11.12 Key Input Interrupt The key input interrupt is enabled by setting ports P10_4 to P10_7 as input ports. The interrupt request is generated if any of the signals applied to ports P10_4 to P10_7 switches from high ...
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R32C/117 Group 11.13 Intelligent I/O Interrupt The intelligent I/O interrupt is assigned to software interrupt numbers from 44 to 55. Figure 11.12 shows a block diagram of the intelligent I/O interrupt. Figure 11.13 and Figure 11.14 show registers IIOiIR and ...
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R32C/117 Group Intelligent I/O Interrupt Request Register Symbol 0 IIO0IR to IIO11IR Bit Symbol (Note 2) (Note 2) (Note 2) (Note 2) (Note 2) (Note 2) Notes: 1. When the register ...
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R32C/117 Group Intelligent I/O Interrupt Enable Register Symbol 0 IIO0IE to IIO11IE Bit Symbol (Note 1) (Note 1) (Note 1) (Note 1) (Note 1) (Note 1) Notes: 1. Refer to the ...
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R32C/117 Group 11.14 Notes on Interrupts 11.14.1 ISP Setting The interrupt stack pointer (ISP) is initialized to 00000000h after a reset. Set a value to the ISP before an interrupt is accepted, otherwise the program may go out of control. ...
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R32C/117 Group 12. Watchdog Timer The watchdog timer monitors program executions and detects defective programs. The 15-bit watchdog counter counts downward with the cycle which is the peripheral bus clock frequency divided by the prescaler. When the watchdog timer underflows, ...
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R32C/117 Group Peripheral bus clock HOLD Write to WDTS register RESET CM06: Bit in the CM0 Register WDC7: Bit in the WDC Register Figure 12.1 Watchdog Timer Block Diagram Watchdog Timer Control Register ...
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R32C/117 Group 13. DMAC Direct Memory Access (DMA system that can control data transfer without using the CPU. The R32C/100 Series’ four channel DMA controller (DMAC) transmits 8-bit (byte), 16-bit (word), or 32-bit (long word) data in cycle-steal ...
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R32C/117 Group Table 13.1 DMAC Specifications Item Channels Bus request mode Transfer memory spaces Maximum transfer bytes (1) DMA request sources Channel priority Transfer sizes Addressing modes Transfer modes Single transfer Repeat transfer DMA transfer complete interrupt request generation timing ...
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R32C/117 Group The DMA transfer request is available by two different sources: software and hardware. More concretely, they are a write access to the DSR bit in the DMiSL2 register ( and an interrupt request output ...
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R32C/117 Group DMAi Request Source Select Register Symbol DM0SL2 to DM3SL2 Bit Symbol DSEL20 DSEL21 DSEL22 DSEL23 DSEL24 (b7-b6) Note: 1. The bit settings of bits DSEL24 to DSEL20 should be ...
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R32C/117 Group Table 13.2 DMiSL Register ( Functions Setting Value DMA0 Select from DMiSL2 register Falling edge of INT0 0 0 ...
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R32C/117 Group Table 13.3 DMiSL2 Register ( Functions Setting Value DMA0 Software trigger Falling edge of INT6 ...
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R32C/117 Group DMAi Mode Register ( b31 b24 b23 b16 b15 Bit Symbol (b7-b6) (b31-b8) Notes: 1. The LDC instruction should be used to write ...
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R32C/117 Group DMAi Terminal Count Reload Register b31 b24 b23 b16 b15 00000000 Set the transfers to be performed Reserved Note: 1. The LDC instruction should be used to write to this register. The register should be ...
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R32C/117 Group DMAi Source Address Reload Register b31 b24 b23 b16 b15 Set a source address Note: 1. The LDC instruction should be used to write to this register. The register should be set while bits MDi1 ...
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R32C/117 Group 13.1 Transfer Cycle The transfer cycle is composed of bus cycles to read data from memory or SFR (source read) and to write data to destination address (destination write). The read and write bus cycles vary with the ...
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R32C/117 Group 13.1.2 Effect of Bus Timing In the R32C/100 Series, each device has its own bus addresses assigned. The bus width and bus timing vary with each device. Table 13.5 lists the bus width and access cycles for each ...
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R32C/117 Group (1) One bus cycle of source-read is generated Example: 16-bit data transfer from the address 8n of the RAM CPU clock CPU address bus CPU occupied CPU data bus CPU occupied CPU RD signal CPU WR signal (2) ...
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R32C/117 Group 13.2 DMA Transfer Cycle The DMA transfer cycles are calculated as follows: Number of a transfer cycles where access cycles for read access cycles for write (refer to Table 13.5) Each bus cycle, source-read, ...
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R32C/117 Group 13.3 Channel Priority and DMA Transfer Timing When multiple DMA transfer requests are generated in the same sampling period, between the falling edge of the CPU clock and the next falling edge, these requests are simultaneously input into ...
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R32C/117 Group 13.4 Notes on DMAC 13.4.1 DMAC-associated Register Settings • Set the DMAC-associated registers while bits MDi1 and MDi0 ( the DMDi register are 00b (DMA transfer disabled). Then, set bits MDi1 and MDi0 ...