AT90S2313-4SI Atmel, AT90S2313-4SI Datasheet - Page 43

• Manufacturer Part Number: AT90S2313-4SI
• Description: MCU 2K FLASH 4MHZ 20-SOIC
• Manufacturer: Atmel
• Series: AVR® 90Sr

Specifications of AT90S2313-4SI

• Core Processor: AVR
• Core Size: 8-Bit
• Speed: 4MHz
• Connectivity: SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, POR, PWM, WDT
• Number Of I /o: 15
• Program Memory Size: 2KB (1K x 16)
• Program Memory Type: FLASH
• Eeprom Size: 128 x 8
• Ram Size: 128 x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 6 V
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 20-SOIC (7.5mm Width)
• Data Bus Width: 8 bit
• Data Ram Size: 128 B
• Interface Type: SPI, UART
• Maximum Clock Frequency: 4 MHz
• Number Of Programmable I/os: 15
• Number Of Timers: 1 x 8 bit
• Operating Supply Voltage: 2.7 V to 6 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• Minimum Operating Temperature: - 40 C
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Data Converters: -
• Lead Free Status / Rohs Status: No

Data Reception
0839I–AVR–06/02
tus Register (USR) is set. When this bit is set (one), the UART is ready to receive the
next character. At the same time as the data is transferred from UDR to the 10(11)-bit
Shift Register, bit 0 of the Shift Register is cleared (start bit) and bit 9 or 10 is set (stop
bit). If 9-bit data word is selected (the CHR9 bit in the UART Control Register [UCR] is
set), the TXB8 bit in UCR is transferred to bit 9 in the Transmit Shift Register.
On the Baud Rate clock following the transfer operation to the Shift Register, the start bit
is shifted out on the TXD pin. Then follows the data, LSB first. When the stop bit has
been shifted out, the Shift Register is loaded if any new data has been written to the
UDR during the transmission. During loading, UDRE is set. If there is no new data in the
UDR Register to send when the stop bit is shifted out, the UDRE Flag will remain set
until UDR is written again. When no new data has been written, and the stop bit has
been present on TXD for one bit length, the TX Complete Flag (TXC) in USR is set.
The TXEN bit in UCR enables the UART transmitter when set (one). When this bit is
cleared (zero), the PD1 pin can be used for general I/O. When TXEN is set, the UART
Transmitter will be connected to PD1, which is forced to be an output pin regardless of
the setting of the DDD1 bit in DDRD.
Figure 35 shows a block diagram of the UART Receiver.
Figure 35. UART Receiver
The Receiver front-end logic samples the signal on the RXD pin at a frequency of 16
times the baud rate. While the line is idle, one single sample of logical “0” will be inter-
preted as the falling edge of a start bit, and the start bit detection sequence is initiated.
Let sample 1 denote the first zero-sample. Following the 1-to-0 transition, the receiver
samples the RXD pin at samples 8, 9 and 10. If two or more of these three samples are
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