AT90S8515A-8JC Atmel, AT90S8515A-8JC Datasheet
AT90S8515A-8JC
Specifications of AT90S8515A-8JC
Related parts for AT90S8515A-8JC
AT90S8515A-8JC Summary of contents
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Features ® • Utilizes the AVR RISC Architecture • AVR – High-performance and Low-power RISC Architecture – 118 Powerful Instructions – Most Single Clock Cycle Execution – General-purpose Working Registers – MIPS Throughput at ...
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Pin Configurations AT90S8515 2 0841G–09/01 ...
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Description Block Diagram 0841G–09/01 The AT90S8515 is a low-power CMOS 8-bit microcontroller based on the AVR RISC architecture. By executing powerful instructions in a single clock cycle, the AT90S8515 achieves throughputs approaching 1 MIPS per MHz, allowing the system designer ...
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... In-System through an SPI serial interface conventional nonvolatile memory programmer. By combining an enhanced RISC 8-bit CPU with In-System Pro- grammable Flash on a monolithic chip, the Atmel AT90S8515 is a powerful microcontroller that provides a highly flexible and cost-effective solution to many embed- ded control applications. ...
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RESET XTAL1 XTAL2 ICP OC1B ALE 0841G–09/01 current if the pull-up resistors are activated. The Port D pins are tri-stated when a reset condition becomes active, even if the clock is not active. Port D also serves the functions of ...
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Crystal Oscillator AT90S8515 6 XTAL1 and XTAL2 are input and output, respectively inverting amplifier that can be configured for use as an on-chip oscillator, as shown in Figure 2. Either a quartz crystal or a ceramic resonator may ...
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Architectural Overview 0841G–09/01 The fast-access register file concept contains 32 x 8-bit general-purpose working regis- ters with a single clock cycle access time. This means that during one single clock cycle, one ALU (Arithmetic Logic Unit) operation is executed. Two ...
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AT90S8515 8 Figure 4. The AT90S8515 AVR RISC Architecture Program Counter Program Memory Instruction Register Instruction Decoder Control Lines A flexible interrupt module has its control registers in the I/O space with an additional global interrupt enable ...
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Figure 5. Memory Maps Program Memory Program FLASH (4K x 16) AT90S8515 Data Memory $000 32 Gen. Purpose Working Registers $001F 64 I/O Registers Internal SRAM (512 x 8) External SRAM (0 - 64K x 8) $FFF $0000 $0020 ...
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General-purpose Register File X-register, Y-register and Z-register AT90S8515 10 Figure 6 shows the structure of the 32 general-purpose working registers in the CPU. Figure 6. AVR CPU General-purpose Working Registers 7 General Purpose Working Registers All the register operating instructions ...
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ALU – Arithmetic Logic Unit In-System Programmable Flash Program Memory 0841G–09/01 In the different addressing modes these address registers have functions as fixed dis- placement, automatic increment and decrement (see the descriptions for the different instructions). The high-performance AVR ALU ...
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SRAM Data Memory – Internal and External AT90S8515 12 Figure 8 shows how the AT90S8515 SRAM memory is organized. Figure 8. SRAM Organization Register File … R29 R30 R31 I/O Registers $00 $01 $02 … $3D $3E ...
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Program and Data Addressing Modes Register Direct, Single Register RD 0841G–09/01 two additional clock cycles is used per byte. This has the following effect: Data transfer instructions take two extra clock cycles, whereas interrupt, subroutine calls and returns will need ...
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Register Direct, Two Registers Rd and Rr I/O Direct Data Direct AT90S8515 14 Figure 10. Direct Register Addressing, Two Registers Operands are contained in register r (Rr) and d (Rd). The result is stored in register d (Rd). Figure 11. ...
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Data Indirect with Displacement Data Indirect Data Indirect with Pre- decrement 0841G–09/01 A 16-bit data address is contained in the 16 LSBs of a 2-word instruction. Rd/Rr specify the destination or source register. Figure 13. Data Indirect with Displacement Operand ...
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Data Indirect with Post- increment Constant Addressing Using the LPM Instruction AT90S8515 16 The X-, Y-, or the Z-register is decremented before the operation. Operand address is the decremented contents of the X-, Y-, or the Z-register. Figure 16. Data ...
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Indirect Program Addressing, IJMP and ICALL Relative Program Addressing, RJMP and RCALL EEPROM Data Memory Memory Access Times and Instruction Execution Timing 0841G–09/01 Figure 18. Indirect Program Memory Addressing 15 Z-REGISTER Program execution continues at address contained by the Z-register ...
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AT90S8515 18 Figure 20. The Parallel Instruction Fetches and Instruction Executions T1 System Clock Ø 1st Instruction Fetch 1st Instruction Execute 2nd Instruction Fetch 2nd Instruction Execute 3rd Instruction Fetch 3rd Instruction Execute 4th Instruction Fetch Figure 21 shows the ...
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I/O Memory 0841G–09/01 The I/O space definition of the AT90S8515 is shown in Table 1. Table 1. AT90S8515 I/O Space Address Hex Name Function $3F ($5F) SREG Status Register $3E ($5E) SPH Stack Pointer High $3D ($5D) SPL Stack Pointer ...
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Status Register – SREG AT90S8515 20 Table 1. AT90S8515 I/O Space (Continued) Address Hex Name Function $11 ($31) DDRD Data Direction Register, Port D $10 ($30) PIND Input Pins, Port D $0F ($2F) SPDR SPI I/O Data Register $0E ($2E) ...
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Stack Pointer – SP 0841G–09/01 into T by the BST instruction and a bit in T can be copied into a bit in a register in the register file by the BLD instruction. • Bit 5 – H: Half-carry Flag ...
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Reset and Interrupt Handling AT90S8515 22 The AT90S8515 provides 12 different interrupt sources. These interrupts and the sepa- rate reset vector each have a separate program vector in the program memory space. All interrupts are assigned individual enable bits that ...
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Reset Sources 0841G–09/01 $00f ldi r16,low(RAMEND) $010 out SPL,r16 $011 <instr> … … … The AT90S8515 has three sources of reset: • Power-on Reset. The MCU is reset when the supply voltage is below the Power-on Reset threshold (V ). ...
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Power-on Reset AT90S8515 24 The user can select the start-up time according to typical oscillator start-up. The number of WDT oscillator cycles used for each time-out is shown in Table 4. The frequency of the Watchdog Oscillator is voltage-dependent as ...
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External Reset Watchdog Reset Interrupt Handling 0841G–09/01 An external reset is generated by a low level on the RESET pin. Reset pulses longer than 50 ns will generate a reset, even if the clock is not running. Shorter pulses are ...
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General Interrupt Mask Register – GIMSK General Interrupt Flag Register – GIFR AT90S8515 26 interrupt. Some of the interrupt flags can also be cleared by writing a logical “1” to the flag bit position( cleared interrupt ...
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Timer/Counter Interrupt Mask Register – TIMSK 0841G–09/01 • Bit 6 – INTF0: External Interrupt Flag0 When an edge on the INT0 pin triggers an interrupt request, the corresponding interrupt flag, INTF0, becomes set (one). If the I-bit in SREG and ...
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Timer/Counter Interrupt Flag Register – TIFR AT90S8515 28 Bit $38 ($58) TOV1 OCF1A OCIFB Read/Write R/W R/W R/W Initial Value • Bit 7 – TOV1: Timer/Counter1 Overflow Flag The TOV1 is set (one) when ...
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External Interrupts Interrupt Response Time MCU Control Register – MCUCR 0841G–09/01 The external interrupts are triggered by the INT1 and INT0 pins. Observe that, if enabled, the interrupts will trigger even if the INT0/INT1 pins are configured as outputs. This ...
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AT90S8515 30 • Bit 5 – SE: Sleep Enable The SE bit must be set (one) to make the MCU enter the Sleep Mode when the SLEEP instruction is executed. To avoid the MCU entering the Sleep Mode, unless it ...
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Sleep Modes Idle Mode Power-down Mode 0841G–09/01 To enter the sleep modes, the SE bit in MCUCR must be set (one) and a SLEEP instruc- tion must be executed enabled interrupt occurs while the MCU ...
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Timer/Counters Timer/Counter Prescaler 8-bit Timer/Counter0 AT90S8515 32 The AT90S8515 provides two general-purpose Timer/Counters – one 8-bit T/C and one 16-bit T/C. The Timer/Counters have individual prescaling selection from the same 10- bit prescaling timer. Both Timer/Counters can either be used ...
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Timer/Counter0 Control Register – TCCR0 0841G–09/01 Figure 29. Timer/Counter0 Block Diagram Bit $33 ($53) – – – Read/Write Initial Value • Bits 7..3 – Res: Reserved Bits These bits are reserved ...
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Timer Counter0 – TCNT0 16-bit Timer/Counter1 AT90S8515 34 The Stop condition provides a Timer Enable/Disable function. The CK down divided modes are scaled directly from the CK oscillator clock. If the external pin modes are used for Timer/Counter0, transitions on ...
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TCCR1B). The interrupt enable/disable settings for Timer/Counter1 are found in the Timer/Counter Interrupt Mask Register (TIMSK). When Timer/Counter1 is externally clocked, the external signal is synchronized with the oscillator frequency of the CPU. To assure proper sampling ...
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Timer/Counter1 Control Register A – TCCR1A AT90S8515 36 Bit $2F ($4F) COM1A1 COM1A0 COM1B1 Read/Write R/W R/W R/W Initial Value • Bits 7, 6 – COM1A1, COM1A0: Compare Output Mode1A, Bits 1 and 0 ...
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Timer/Counter1 Control Register B – TCCR1B 0841G–09/01 Bit $2E ($4E) ICNC1 ICES1 – Read/Write R/W R/W R Initial Value • Bit 7 – ICNC1: Input Capture1 Noise Canceler (4 CKs) When the ICNC1 bit ...
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Timer/Counter1 – TCNT1H AND TCNT1L Timer/Counter1 Output Compare Register – OCR1AH AND OCR1AL AT90S8515 38 The Stop condition provides a Timer Enable/Disable function. The CK down divided modes are scaled directly from the CK oscillator clock. If the external pin ...
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Timer/Counter1 Output Compare Register – OCR1BH AND OCR1BL Timer/Counter1 Input Capture Register – ICR1H AND ICR1L 0841G–09/01 Bit $29 ($49) MSB $28 ($48 Read/Write R/W R/W R/W R/W R/W R/W Initial Value 0 0 ...
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Timer/Counter1 in PWM Mode AT90S8515 40 The TEMP register is also used when accessing TCNT1, OCR1A and OCR1B. If the main program and interrupt routines perform access to registers using TEMP, interrupts must be disabled during access from the main ...
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Figure 32. Effects on Unsynchronized OCR1 Latching Compare Value changes Synchronized Compare Value changes Unsynchronized Note During the time between the write and the latch operation, a read from OCR1A or OCR1B will read ...
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Watchdog Timer Watchdog Timer Control Register – WDTCR AT90S8515 42 The Watchdog Timer is clocked from a separate On-chip oscillator that runs at 1 MHz. This is the typical value 5V. See characterization data for typical values ...
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In the same operation, write a logical “1” to WDTOE and WDE. A logical “1” must be written to WDE even though it is set to one before the disable operation starts. 2. Within the next four clock ...
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EEPROM Read/Write Access EEPROM Address Register – EEARH and EEARL EEPROM Data Register – EEDR EEPROM Control Register – EECR AT90S8515 44 The EEPROM access registers are accessible in the I/O space. The write access time is in the range ...
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Bit 2 – EEMWE: EEPROM Master Write Enable The EEMWE bit determines whether setting EEWE to one causes the EEPROM to be written. When EEMWE is set (one), setting EEWE will write data to the EEPROM at the ...
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Prevent EEPROM Corruption AT90S8515 46 During periods of low V , the EEPROM data can be corrupted because the supply volt- CC age is too low for the CPU and the EEPROM to operate properly. These issues are the same ...
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Serial Peripheral Interface – SPI 0841G–09/01 The Serial Peripheral Interface (SPI) allows high-speed synchronous data transfer between the AT90S8515 and peripheral devices or between several AVR devices. The AT90S8515 SPI features include the following: • Full-duplex, 3-wire Synchronous Data Transfer ...
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SS Pin Functionality AT90S8515 48 Figure 35. SPI Master-slave Interconnection MSB MASTER 8-BIT SHIFT REGISTER SPI CLOCK GENERATOR The system is single-buffered in the transmit direction and double-buffered in the receive direction. This means that bytes to be transmitted cannot ...
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Data Modes SPI Control Register – SPCR 0841G–09/01 pins are inputs. When SS is driven high, all pins are inputs and the SPI is passive, which means that it will not receive incoming data. Note that the SPI logic will ...
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SPI Status Register – SPSR AT90S8515 50 • Bit 5 – DORD: Data Order When the DORD bit is set (one), the LSB of the data word is transmitted first. When the DORD bit is cleared (zero), the MSB of ...
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SPI Data Register – SPDR 0841G–09/01 Bit $0F ($2F) MSB Read/Write R/W R/W R/W Initial Value The SPI Data Register is a read/write register used for data transfer between the regis- ter file and ...
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UART Data Transmission AT90S8515 52 The AT90S8515 features a full duplex (separate receive and transmit registers) Univer- sal Asynchronous Receiver and Transmitter (UART). The main features are: • Baud Rate Generator that can Generate a large Number of Baud Rates ...
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Data Reception 0841G–09/01 If the 10(11)-bit Transmitter shift register is empty, data is transferred from UDR to the shift register. At this time the UDRE (UART Data Register Empty) bit in the UART Status Register, USR, is set. When this ...
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AT90S8515 54 The receiver front-end logic samples the signal on the RXD pin at a frequency 16 times the baud rate. While the line is idle, one single sample of logical “0” will be interpreted as the falling edge of ...
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UART Control UART I/O Data Register – UDR UART Status Register – USR 0841G–09/01 Bit $0C ($2C) MSB Read/Write R/W R/W R/W Initial Value The UDR register is actually two physically separate registers sharing ...
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UART Control Register – UCR AT90S8515 56 The FE bit is cleared when the stop bit of received data is one. • Bit 3 – OR: Overrun This bit is set if an Overrun condition is detected, i.e., when a ...
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BAUD Rate Generator 0841G–09/01 The baud rate generator is a frequency divider that generates baud rates according to the following equation: BAUD • BAUD = Baud rate • Crystal Clock frequency CK • UBRR = Contents of the ...
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Table 17. UBRR Settings at Various Crystal Frequencies Baud Rate 1 MHz %Error 2400 UBRR= 25 4800 UBRR= 12 9600 UBRR= 6 14400 UBRR= 3 19200 UBRR= 2 28800 UBRR= 1 38400 UBRR= 1 57600 UBRR= 0 76800 UBRR= 0 ...
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Analog Comparator Analog Comparator Control and Status Register – ACSR 0841G–09/01 The Analog Comparator compares the input values on the positive input PB2 (AIN0) and negative input PB3 (AIN1). When the voltage on the positive input PB2 (AIN0) is higher ...
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Interface to External SRAM AT90S8515 60 using the SBI or CBI instruction, ACI will be cleared if it has become set before the operation. • Bit 3 – ACIE: Analog Comparator Interrupt Enable When the ACIE bit is set (one) ...
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Default, the external SRAM access 3-cycle scheme as depicted in Figure 43. When one extra wait state is needed in the access cycle, set the SRW bit (one) in the MCUCR register. The resulting access scheme is ...
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AT90S8515 62 Figure 44. External Data SRAM Memory Cycles with Wait State T1 System Clock Ø ALE Address [15..8] Prev. Address Data/Address [7..0] Prev. Address WR Data/Address [7..0] Prev. Address Address Address Data Address Data T4 Addr. ...
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I/O Ports Port A Port A Data Register – PORTA Port A Data Direction Register – DDRA Port A Input Pins Address – PINA Port A as General Digital I/O 0841G–09/01 All AVR ports have true read-modify-write functionality when used ...
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Port A Schematics AT90S8515 64 PORTAn has to be cleared (zero) or the pin has to be configured as an output pin. The Port A pins are tri-stated when a reset condition becomes active, even if the clock is not ...
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Port B Port B Data Register – PORTB Port B Data Direction Register – DDRB Port B Input Pins Address – PINB 0841G–09/01 Port 8-bit bi-directional I/O port. Three I/O memory address locations are allocated for the ...
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Port B as General Digital I/O Alternate Functions of Port B AT90S8515 66 All eight pins in Port B have equal functionality when used as digital I/O pins. PBn, general I/O pin: The DDBn bit in the DDRB register selects ...
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Port B Schematics 0841G–09/01 • AIN0 – Port B, Bit 2 AIN0: Analog Comparator Positive Input. When configured as an input (DDB2 is cleared [zero]) and with the internal MOS pull-up resistor switched off (PB2 is cleared [zero]), this pin ...
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AT90S8515 68 Figure 47. Port B Schematic Diagram (Pins PB2 and PB3) Figure 48. Port B Schematic Diagram (Pin PB4) MOS PULL- UP PB4 WRITE PORTB WP: WD: WRITE DDRB RL: READ PORTB LATCH RP: READ PORTB PIN RD: READ ...
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Figure 49. Port B Schematic Diagram (Pin PB5) MOS PULL- UP PB5 WRITE PORTB WP: WD: WRITE DDRB RL: READ PORTB LATCH RP: READ PORTB PIN RD: READ DDRB SPI ENABLE SPE: MSTR MASTER SELECT Figure 50. Port B ...
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Port C Port C Data Register – PORTC AT90S8515 70 Figure 51. Port B Schematic Diagram (Pin PB7) MOS PULL- UP PB7 WRITE PORTB WP: WD: WRITE DDRB RL: READ PORTB LATCH RP: READ PORTB PIN READ DDRB RD: SPE: ...
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Port C Data Direction Register – DDRC Port C Input Pins Address – PINC Port C as General Digital I/O 0841G–09/01 Bit $14 ($34) DDC7 DDC6 DDC5 Read/Write R/W R/W R/W Initial Value Bit ...
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Port C Schematics Port D AT90S8515 72 Note that all port pins are synchronized. The synchronization latch is, however, not shown in the figure. Figure 52. Port C Schematic Diagram (Pins PC0 - PC7) Port 8-bit bi-directional ...
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Port D Data Register – PORTD Port D Data Direction Register – DDRD Port D Input Pins Address – PIND Port D as General Digital I/O Alternate Functions of Port D 0841G–09/01 Bit $12 ($32) PORTD7 PORTD6 ...
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Port D Schematics AT90S8515 74 • INT1 – Port D, Bit 3 INT1: External Interrupt source 1. The PD3 pin can serve as an external interrupt source to the MCU. See the interrupt description for further details and how to ...
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Figure 54. Port D Schematic Diagram (Pin PD1) MOS PULL- UP PD1 WP: WRITE PORTD WD: WRITE DDRD RL: READ PORTD LATCH RP: READ PORTD PIN RD: READ DDRD TXD: UART TRANSMIT DATA UART TRANSMIT ENABLE TXEN: Figure 55. ...
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AT90S8515 76 Figure 56. Port D Schematic Diagram (Pin PD4) Figure 57. Port D Schematic Diagram (Pin PD5) 0841G–09/01 ...
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Figure 58. Port D Schematic Diagram (Pin PD6) Figure 59. Port D Schematic Diagram (Pin PD7) AT90S8515 77 ...
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... The Fuse bits are not accessible in Serial Programming Mode. The status of the Fuse bits is not affected by Chip Erase. All Atmel microcontrollers have a three-byte signature code that identifies the device. This code can be read in both Serial and Parallel mode. The three bytes reside in a sep- arate address space ...
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Parallel Programming Signal Names 0841G–09/01 the self-timed write operation in the serial programming mode. During programming, the supply voltage must be in accordance with Table 26. Table 26. Supply Voltage during Programming Part Serial Programming AT90S8515 2.7 - 6.0V This ...
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Enter Programming Mode AT90S8515 80 Table 27. Pin Name Mapping Signal Name in Programming Mode Pin Name BSY RDY/ PD1 OE PD2 WR PD3 BS PD4 XA0 PD5 XA1 PD6 DATA PB7-0 Table 28. XA1 and XA0 Coding XA1 XA0 ...
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Chip Erase Programming the Flash 0841G–09/01 The Chip Erase command will erase the Flash and EEPROM memories and the Lock bits. The Lock bits are not reset until the Flash and EEPROM have been completely erased. The Fuse bits are ...
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AT90S8515 82 1. Set BS to “1”. This selects high data. 2. Give WR a negative pulse. This starts programming of the data byte. RDY/BSY goes low. 3. Wait until RDY/BSY goes high to program the next byte. (See Figure ...
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Reading the Flash Programming the EEPROM Reading the EEPROM Programming the Fuse Bits 0841G–09/01 Figure 62. Programming the Flash Waveforms (Continued) DATA DATA HIGH XA1 XA0 BS XTAL1 WR RDY/BSY RESET +12V OE The algorithm for reading the Flash memory ...
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Programming the Lock Bits Reading the Fuse and Lock Bits Reading the Signature Bytes AT90S8515 84 Bit 5 = SPIEN Fuse bit Bit 0 = FSTRT Fuse bit Bit “1”. These bits are ...
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Parallel Programming Characteristics 0841G–09/01 Figure 63. Parallel Programming Timing t XTAL1 XHXL t DVXH Data & Control (DATA, XA0/1, BS) WR RDY/BSY OE DATA Table 30. Parallel Programming Characteristics, T Symbol Parameter V Programming Enable Voltage PP I Programming Enable ...
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Serial Downloading Serial Programming Algorithm AT90S8515 86 Both the program and data memory arrays can be programmed using the SPI bus while RESET is pulled to GND. The serial interface consists of pins SCK, MOSI (input) and MISO (output). See ...
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Data Polling EEPROM Data Polling Flash 0841G–09/01 ing the third byte of the Programming Enable instruction. Whether the echo is correct or not, all four bytes of the instruction must be transmitted. If the $53 did not echo back, give ...
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Table 32. Serial Programming Instruction Set Instruction Byte 1 1010 1100 Programming Enable 1010 1100 Chip Erase 0010 H000 Read Program Memory 0100 H000 Write Program Memory 1010 0000 Read EEPROM Memory 1100 0000 Write EEPROM Memory 1010 1100 Write ...
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Serial Programming Characteristics 0841G–09/01 Figure 66. Serial Programming Timing MOSI t OVSH SCK MISO Table 33. Serial Programming Characteristics, T (unless otherwise noted) Symbol Parameter 1/t Oscillator Frequency (V CLCL t Oscillator Period (V = 2.7 - 4.0V) CLCL CC ...
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Electrical Characteristics Absolute Maximum Ratings* Operating Temperature.................................. -55°C to +125°C Storage Temperature ..................................... -65°C to +150°C Voltage on Any Pin except RESET with Respect to Ground .............................-1. Voltage on RESET with Respect to Ground ...................................-1.0V to +13.0V Maximum ...
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Notes: 1. “Max” means the highest value where the pin is guaranteed to be read as low. 2. “Min” means the lowest value where the pin is guaranteed to be read as high. 3. Although each I/O port can sink ...
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External Clock Drive Waveforms AT90S8515 92 Figure 67. External Clock VIH1 VIL1 Table 36. External Clock Drive Symbol Parameter 1/t Oscillator Frequency CLCL t Clock Period CLCL t High Time CHCX t Low Time CLCX t Rise Time CLCH t ...
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External Data Memory Timing Table 37. External Data Memory Characteristics, 4.0V - 6.0V, No Wait State Symbol Parameter 0 1/t Oscillator Frequency CLCL 1 t ALE Pulse Width LHLL 2 t Address Valid A to ALE Low AVLL Address Hold ...
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Table 39. External Data Memory Characteristics, 2.7V - 4.0V, No Wait State Symbol Parameter 0 1/t Oscillator Frequency CLCL 1 t ALE Pulse Width LHLL 2 t Address Valid A to ALE Low AVLL Address Hold after ALE Low, 3a ...
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Typical Characteristics 0841G–09/01 The following charts show typical behavior. These figures are not tested during manu- facturing. All current consumption measurements are performed with all I/O pins configured as inputs and with internal pull-ups enabled. ICP is pulled high externally. ...
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AT90S8515 96 Figure 70. Active Supply Current vs. V ACTIVE SUPPLY CURRENT vs 2.5 3 3.5 Figure 71. Idle Supply Current vs. Frequency IDLE SUPPLY CURRENT vs. FREQUENCY 12 10 ...
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Figure 72. Idle Supply Current vs. V IDLE SUPPLY CURRENT vs 3.5 3 2.5 2 1 2.5 3 Figure 73. Power-down Supply Current vs. V POWER DOWN SUPPLY CURRENT vs. V WATCHDOG TIMER ...
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AT90S8515 98 Figure 74. Power-down Supply Current vs. V POWER DOWN SUPPLY CURRENT vs. V WATCHDOG TIMER ENABLED 140 120 100 2.5 3 3.5 Figure 75. Analog Comparator Current vs. V ANALOG COMPARATOR CURRENT ...
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Analog Comparator offset voltage is measured as absolute offset. Figure 76. Analog Comparator Offset Voltage vs. Common Mode Voltage ANALOG COMPARATOR OFFSET VOLTAGE vs. COMMON MODE VOLTAGE 0.5 ...
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AT90S8515 100 Figure 78. Analog Comparator Input Leakage Current ANALOG COMPARATOR INPUT LEAKAGE CURRENT -10 0 0.5 1 1.5 2 2.5 Figure 79. Watchdog Oscillator Frequency vs. V WATCHDOG OSCILLATOR FREQUENCY vs. V ...
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Sink and source capabilities of I/O ports are measured on one pin at a time. Figure 80. Pull-up Resistor Current vs. Input Voltage PULL-UP RESISTOR CURRENT vs. INPUT VOLTAGE 120 ˚ A 100 T = ...
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AT90S8515 102 Figure 82. I/O Pin Sink Current vs. Output Voltage I/O PIN SINK CURRENT vs. OUTPUT VOLTAGE 0.5 1 Figure 83. I/O Pin Source Current vs. Output Voltage I/O PIN ...
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Figure 84. I/O Pin Source Current vs. Output Voltage I/O PIN SOURCE CURRENT vs. OUTPUT VOLTAGE ˚ ˚ 0.5 1 Figure ...
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AT90S8515 104 Figure 86. I/O Pin Input Hysteresis vs. V I/O PIN INPUT HYSTERESIS vs. V 0.18 0.16 0.14 0.12 0.1 0.08 0.06 0.04 0.02 0 2.7 Figure 87. I/O Pin Sink Current vs. Output Voltage I/O PIN SINK CURRENT ...
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Register Summary Address Name Bit 7 $3F ($5F) SREG I $3E ($5E) SPH SP15 $3D ($5D) SPL SP7 $3C ($5C) Reserved $3B ($5B) GIMSK INT1 $3A ($5A) GIFR INTF1 $39 ($59) TIMSK TOIE1 $38 ($58) TIFR TOV1 $37 ($57) Reserved ...
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Instruction Set Summary Mnemonic Operands Description ARITHMETIC AND LOGIC INSTRUCTIONS ADD Rd, Rr Add Two Registers ADC Rd, Rr Add with Carry Two Registers ADIW Rdl, K Add Immediate to Word SUB Rd, Rr Subtract Two Registers SUBI Rd, K ...
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Instruction Set Summary (Continued) Mnemonic Operands Description DATA TRANSFER INSTRUCTIONS MOV Rd, Rr Move between Registers LDI Rd, K Load Immediate LD Rd, X Load Indirect LD Rd, X+ Load Indirect and Post-inc. LD Rd, -X Load Indirect and Pre-dec. ...
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... Power Supply 4 2.7V - 6.0V 8 4.0V - 6.0V Note: Order AT90S8515A-XXX for devices with the FSTRT Fuse programmed. 44A 44-lead, Thin (1.0 mm) Plastic Gull Wing Quad Flat Package (TQFP) 44J 44-lead, Plastic J-leaded Chip Carrier (PLCC) 40P6 40-lead, 0.600" Wide, Plastic Dual Inline Package (PDIP) ...
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Packaging Information 44A 44-lead, Thin (1.0mm) Plastic Quad Flat Package (TQFP), 10x10mm body, 2.0mm footprint, 0.8mm pitch. Dimension in Millimeters and (Inches)* JEDEC STANDARD MS-026 ACB 0.80(0.0315) BSC 0.20(0.008) 0.09(0.004) REV. A 04/11/2001 0841G–09/01 PIN 1 ID PIN 1 0˚~7˚ ...
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Plastic J-leaded Chip Carrier (PLCC) Dimensions in Milimeters and (Inches)* JEDEC STANDARD MS-018 AC 1.14(0.045) X 45˚ 0.813(0.032) 0.660(0.026) 1.27(0.050) TYP REV. A 04/11/2001 AT90S8515 110 1.14(0.045) X 45˚ PIN NO. 1 IDENTIFY 16.70(0.656) SQ 16.50(0.650) 17.70(0.695) ...
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Plastic Dual Inline Parkage (PDIP), 0.600" wide Demension in Millimeters and (Inches)* JEDEC STANDARD MS-011 AC 4.83(0.190)MAX SEATING PLANE 3.56(0.140) 3.05(0.120) 2.54(0.100)BSC 0.38(0.015) 0.20(0.008) REV. A 04/11/2001 0841G–09/01 52.71(2.075) 51.94(2.045) 48.26(1.900) REF 1.65(0.065) 1.27(0.050) 15.88(0.625) 15.24(0.600) 0º ~ ...
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... No licenses to patents or other intellectual property of Atmel are granted by the Company in connection with the sale of Atmel products, expressly or by implication. Atmel’s products are not authorized for use as critical components in life support devices or systems. ...