ATMEGA163L-4AC Atmel, ATMEGA163L-4AC Datasheet
ATMEGA163L-4AC
Specifications of ATMEGA163L-4AC
Related parts for ATMEGA163L-4AC
ATMEGA163L-4AC Summary of contents
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... Programmable I/O Lines – 40-pin PDIP and 44-pin TQFP • Operating Voltages – 2.7 - 5.5V for ATmega163L – 4.0 - 5.5V for ATmega163 • Speed Grades – MHz for ATmega163L – MHz for ATmega163 ® 8-bit Microcontroller 8-bit Microcontroller with 16K Bytes In-System ...
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Pin Configurations ATmega163(L) 2 (SDA) (SCL) 1142E–AVR–02/03 ...
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Description The ATmega163 is a low-power CMOS 8-bit microcontroller based on the AVR architec- ture. By executing powerful instructions in a single clock cycle, the ATmega163 achieves throughputs approaching 1 MIPS per MHz allowing the system designer to optimize power ...
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... Application Flash memory. By combining an 8-bit CPU with In-System Self-Programmable Flash on a monolithic chip, the Atmel ATmega163 is a powerful microcontroller that provides a highly flexible and cost effective solution to many embedded control applications. ...
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Port C also serves the functions of various special features of the ATmega163 as listed on page 124. Port D (PD7..PD0) Port 8-bit bidirectional I/O port with internal pull-up resistors (selected for each bit). The Port D ...
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Crystal Oscillator XTAL1 and XTAL2 are input and output, respectively inverting amplifier which can be configured for use as an On-chip Oscillator, as shown in Figure 2. Either a quartz crystal or a ceramic resonator may be used. ...
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Architectural The fast-access Register File concept contains 32 x 8-bit general purpose working reg- isters with a single clock cycle access time. This means that during one single clock Overview cycle, one Arithmetic Logic Unit (ALU) operation is executed. Two ...
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Figure 5. The ATmega163 AVR RISC Architecture The AVR uses a Harvard architecture concept – with separate memories and buses for program and data. The Program memory is executed with a two stage pipeline. While one instruction is being executed, ...
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The 1,024 bytes data SRAM can be easily accessed through the five different address- ing modes supported in the AVR architecture. The memory spaces in the AVR architecture are all linear and regular memory maps. A flexible interrupt module has ...
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The General Purpose Figure 7 shows the structure of the 32 general purpose working registers in the CPU. Register File Figure 7. AVR CPU General Purpose Working Registers All the register operating instructions in the instruction set have direct and ...
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In the different addressing modes these address registers have functions as fixed dis- placement, automatic increment and decrement (see the descriptions for the different instructions). The ALU – Arithmetic The high-performance AVR ALU operates in direct connection with all the ...
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The lower 1,120 Data Memory locations address the Register File, the I/O Memory, and the internal data SRAM. The first 96 locations address the Register File + I/O Memory, and the next 1,024 locations address the internal data SRAM. The ...
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Register Direct, Two Registers Figure 11. Direct Register Addressing, Two Registers Rd And Rr Operands are contained in register r (Rr) and d (Rd). The result is stored in register d (Rd). I/O Direct Figure 12. I/O Direct Addressing Operand ...
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Data Indirect with Figure 14. Data Indirect with Displacement Displacement Operand address is the result of the Y- or Z-register contents added to the address con- tained in 6 bits of the instruction word. Data Indirect Figure 15. Data Indirect ...
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Data Indirect with Post- Figure 17. Data Indirect Addressing with Post-increment increment The X-, Y-, or the Z-register is incremented after the operation. Operand address is the content of the X-, Y-, or the Z-register prior to incrementing. Constant Addressing ...
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Relative Program Addressing, Figure 20. Relative Program Memory Addressing RJMP and RCALL Program execution continues at address The relative address k is from -2,048 to 2,047. The EEPROM Data The ATmega163 contains 512 bytes of ...
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Figure 22. Single Cycle ALU Operation The internal data SRAM access is performed in two System Clock cycles as described in Figure 23. Figure 23. On-chip Data SRAM Access Cycles I/O Memory The I/O space definition of the ATmega163 is ...
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Table 2. ATmega163 I/O Space (Continued) ATmega163(L) 18 I/O Address (SRAM Address) Name Function $32 ($52) TCNT0 Timer/Counter0 (8-bit) $31 ($51) OSCCAL Oscillator Calibration Register $30 ($50) SFIOR Special Function I/O Register $2F ($4F) TCCR1A Timer/Counter1 Control Register A $2E ...
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Table 2. ATmega163 I/O Space (Continued) Note: All ATmega163 I/Os and peripherals are placed in the I/O space. The I/O locations are accessed by the IN and OUT instructions, transferring data between the 32 general pur- pose working registers and ...
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The Status Register – SREG The AVR Status Register – SREG – at I/O space location $3F ($5F) is defined as: • Bit 7 – I: Global Interrupt Enable The Global Interrupt Enable bit must be set (one) for the ...
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The Stack Pointer – SP The ATmega163 Stack Pointer is implemented as two 8-bit registers in the I/O space locations $3E ($5E) and $3D ($5D). As the ATmega163 data memory has $460 loca- tions, 11 bits are used. The Stack ...
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Table 3. Reset and Interrupt Vectors (Continued) Note: The most typical and general program setup for the Reset and Interrupt Vector Addresses in ATmega163 is: ATmega163(L) 22 Program Vector No. Address Source 13 $018 UART, UDRE 14 $01A UART, TXC ...
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When the BOOTRST Fuse is programmed and the Boot section size set to 512 bytes, the most typical and general program setup for the Reset and Interrupt Vector Addresses in ATmega163 is: Reset Sources The ATmega163 has four sources of ...
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Figure 24. Reset Logic Table 4. Reset Characteristics (V Notes: ATmega163(L) 24 Power-on VCC Reset Circuit Brown-out BODEN Reset Circuit BODLEVEL 100-500kW SPIKE RESET Reset Circuit FILTER Watchdog Timer On-chip RC Oscillator Clock Generator CKSEL[3:0] CC Symbol Parameter V Power-on ...
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Table 5. Reset Delay Selections Notes: Table 5 shows the Start-up Times from Reset. When the CPU wakes up from Power- down or Power-save, only the clock counting part of the start-up time is used. The Watchdog Oscillator is used ...
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Table 6. Number of Watchdog Oscillator Cycles Note: Power-on Reset A Power-on Reset (POR) pulse is generated by an On-chip detection circuit. The detec- tion level is defined in Table 4. The POR is activated whenever V detection level. The ...
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Figure 26. MCU Start-up, RESET Extended Externally External Reset An External Reset is generated by a low level on the RESET pin. Reset pulses longer than 500 ns will generate a Reset, even if the clock is not running. Shorter ...
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Figure 28. Brown-out Reset During Operation The hysteresis on V Watchdog Reset When the Watchdog times out, it will generate a short reset pulse of 1 XTAL cycle dura- tion. On the falling edge of this pulse, the delay timer ...
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Bit 2 – BORF: Brown-out Reset Flag This bit is set if a Brown-out Reset occurs. The bit is reset by a Power-on Reset writing a logic zero to the Flag. • Bit 1 – EXTRF: External ...
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If one or more interrupt conditions occur when the Global Interrupt Enable bit is cleared (zero), the corresponding interrupt flag(s) will be set and remembered until the Global Interrupt Enable bit is set (one), and will be executed by order ...
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Bits 4..0 – Res: Reserved Bits These bits are reserved bits in the ATmega163 and always read as zero. The General Interrupt Flag Register – GIFR • Bit 7 – INTF1: External Interrupt Flag1 When an edge on the ...
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PD6 (ICP), i.e., when the ICF1 bit is set in the Timer/Counter Interrupt Flag Register – TIFR. • Bit 4 – OCIE1A: Timer/Counter1 Output CompareA Match Interrupt Enable ...
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Timer/Counter2 Overflow Interrupt is executed. In up/down PWM mode, this bit is set when Timer/Counter2 changes counting direction at $00. • Bit 5 – ICF1: Input Capture Flag1 The ICF1 bit is set (one) to Flag an Input Capture Event, ...
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MCU Control Register – The MCU Control Register contains control bits for general MCU functions. MCUCR • Bit 7 – Res: Reserved Bit This bit is a reserved bit in the ATmega163 and always reads as zero. • Bit 6 ...
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Bit 1, 0 – ISC01, ISC00: Interrupt Sense Control 0 Bit 1 and Bit 0 The External Interrupt 0 is activated by the external pin INT0 if the SREG I-Flag and the corresponding interrupt mask are set. The level ...
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Power-down Mode When the SM1/SM0 bits are 10, the SLEEP instruction makes the MCU enter Power- down mode. In this mode, the external Oscillator is stopped, while the external inter- rupts, the Two-wire Serial Interface address match, and the Watchdog ...
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Calibrated Internal RC The calibrated internal Oscillator provides a fixed 1 MHz (nominal) clock at 5V and 25 C. This clock may be used as the system clock. See the section “Clock Options” on Oscillator page 5 for information on ...
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Bit 2 – PUD: Pull-up Disable When this bit is set (one), all pull-ups on all ports are disabled. If the bit is cleared (zero), the pull-ups can be individually enabled as described in the chapter “I/O Ports” on ...
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Timer/Counters The ATmega163 provides three general purpose Timer/Counters – two 8-bit T/Cs and one 16-bit T/C. Timer/Counter2 can optionally be asynchronously clocked from an exter- nal Oscillator. This Oscillator is optimized for use with a 32.768 kHz watch crystal, enabling ...
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Figure 31. Prescaler for Timer/Counter2 The clock source for Timer/Counter2 is named PCK2. PCK2 is by default connected to the main system clock CK. By setting the AS2 bit in ASSR, Timer/Counter2 is asynchro- nously clocked from the PC6(TOSC1) pin. ...
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Figure 32. Timer/Counter0 Block Diagram Timer/Counter0 Control Register – TCCR0 • Bits 7..3 – Res: Reserved Bits These bits are reserved bits in the ATmega163 and always read as zero. • Bits 2..0 – CS02, CS01, CS00: Clock Select0, Bit ...
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Timer/Counter 0 – TCNT0 The Timer/Counter0 is implemented as an up-counter with read and write access. If the Timer/Counter0 is written and a clock source is present, the Timer/Counter0 continues counting in the clock cycle following the write operation. 16-bit ...
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The external clock signal is sampled on the rising edge of the internal CPU clock. The 16-bit Timer/Counter1 features both a high resolution and a high accuracy usage with the lower prescaling opportunities. Similarly, the high prescaling opportunities ...
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Timer/Counter1 Control Register A – TCCR1A • Bits 7, 6 – COM1A1, COM1A0: Compare Output Mode1A, Bits 1, and 0 The COM1A1 and COM1A0 control bits determine any output pin action following a Compare Match in Timer/Counter1. Any output pin ...
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Timer. The automatic action programmed in COM1B1 and COM1B0 happens Compare Match had occurred, but no interrupt is generated. The corresponding I/O pin must be set as an output pin for the FOC1B bit to ...
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When the prescaler is set to divide by eight, the Timer will count like this: ... | C-1, C-1, C-1, C-1, C-1, C-1, C-1, C ...
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TCNT1 Timer/Counter1 Write When the CPU writes to the high byte TCNT1H, the written data is placed in the TEMP Register. Next, when the CPU writes the low byte TCNT1L, this byte of data is combined with the byte data ...
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The TEMP Register is also used when accessing TCNT1 and ICR1. If the main program and also interrupt routines perform access to registers using TEMP, interrupts must be disabled during access from the main program and interrupt routines. Timer/Counter1 Input ...
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Table 15. Timer TOP Values and PWM Frequency As shown in Table 15, the PWM operates at either bits resolution. Note the unused bits in OCR1A, OCR1B, and TCNT1 will automatically be written to zero by ...
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Figure 35. Effects of Unsynchronized OCR1 Latching. Figure 36. Effects of Unsynchronized OCR1 Latching in Overflow Mode. During the time between the write and the latch operation, a read from OCR1A or OCR1B will read the contents of the temporary ...
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In overflow PWM mode, the table above is only valid for OCR1X = TOP. In PWM mode, the Timer Overflow Flag1, TOV1, is set when the counter advances from $00 00. In overflow PWM mode, the Timer Overflow Flag is ...
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The external clock signal is sampled on the rising edge of the internal CPU clock. This module features a high resolution and a high accuracy usage with the lower pres- caling opportunities. Similarly, the high prescaling opportunities make ...
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Bit 3 – CTC2: Clear Timer/Counter on Compare Match When the CTC2 control bit is set (one), Timer/Counter2 is Reset to $00 in the CPU clock cycle following a Compare Match. If the control bit is cleared, the Timer/Counter2 ...
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Timer/Counter2 Output Compare Register – OCR2 The Output Compare Register is an 8-bit read/write register. The Timer/Counter Output Compare Register contains the data to be continuously com- pared with Timer/Counter2. Actions on compare matches are specified in TCCR2. A software ...
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Table 21. Compare Mode Select in PWM Mode Note that in PWM mode, the value to be written to the Output Compare Register is first tr an sfe temp tio n ...
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Figure 39. Effects of Unsynchronized OCR Latching in Overflow Mode. During the time between the write and the latch operation, a read from OCR2 will read the contents of the temporary location. This means that the most recently written value ...
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Asynchronous Status Register – ASSR • Bit 7..4 – Res: Reserved Bits These bits are reserved bits in the ATmega163 and always read as zero. • Bit 3 – AS2: Asynchronous Timer/Counter2 When AS2 is cleared (zero), Timer/Counter2 is clocked ...
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Asynchronous Operation of When Timer/Counter2 operates asynchronously, some considerations must be taken. Timer/Counter2 • • • • • • • ATmega163(L) 58 Warning: When switching between asynchronous and synchronous clocking of Timer/Counter2, the Timer Registers TCNT2, OCR2, and TCCR2 might ...
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After wake-up, the MCU is halted for four clock cycles, ...
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Watchdog Timer The Watchdog Timer is clocked from a separate On-chip Oscillator which runs at 1 MHz. This is the typical value other V interval can be adjusted as shown in Table 23 on page 61. The ...
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In the same operation, write a logical one to WDTOE and WDE. A logical one 2. Within the next four clock cycles, write a logical 0 to WDE. This disables the • Bits 2..0 – WDP2, WDP1, WDP0: Watchdog ...
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EEPROM Read/Write The EEPROM Access Registers are accessible in the I/O space. Access The write access time is in the range of 1.9 - 3.8 ms, depending on the V See Table 24 for details. A self-timing function, however, lets ...
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The EEPROM Control Register – EECR • Bits 7..4 – Res: Reserved Bits These bits are reserved bits in the ATmega163 and will always read as zero. • Bit 3 – EERIE: EEPROM Ready Interrupt Enable When the I bit ...
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The user should poll the EEWE bit before starting the read operation write operation is in progress not possible to set the EERE bit, nor to change the EEAR Register. The calibrated Oscillator is used to ...
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Serial Peripheral The Serial Peripheral Interface (SPI) allows high-speed synchronous data transfer between the ATmega163 and peripheral devices or between several AVR devices. The Interface – SPI ATmega163 SPI includes the following features: • • • • • • • ...
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During one shift cycle, data in the Master and the Slave is interchanged. Figure 42. SPI Master-Slave Interconnection The system is single buffered in the transmit direction and double buffered in the receive direction. This means ...
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When the SPI is configured as a Slave, the SS pin is always input. When SS is held low, the SPI is activated, and MISO becomes an output if configured so by the user. All other pins are inputs. When ...
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Bit 5 – DORD: Data Order When the DORD bit is set (one), the LSB of the data word is transmitted first. When the DORD bit is cleared (zero), the MSB of the data word is transmitted first. • ...
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Bit 6 – WCOL : Write COLlision Flag The WCOL bit is set if the SPI Data Register (SPDR) is written during a data transfer. The WCOL bit (and the SPIF bit) are cleared (zero) by first reading the ...
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UART The ATmega163 features a full duplex (separate Receive and Transmit Registers) Uni- versal Asynchronous Receiver and Transmitter (UART). The main features are: • • • • • • • • • • Data Transmission A block schematic of the ...
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When data is transferred from UDR to the Shift Register, the UDRE (UART Data Regis- ter Empty) bit in the UART Status Register, USR, is set. When this bit is set (one), the UART is ready to receive the next ...
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Data Reception Figure 46 shows a block diagram of the UART Receiver Figure 46. UART Receiver The Receiver front-end logic samples the signal on the RXD pin at a frequency 16 times the baud rate. While the line is idle, ...
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Figure 47. Sampling Received Data Note: When the stop bit enters the Receiver, the majority of the three samples must be one to accept the stop bit. If two or more samples are logical zeros, the Framing Error (FE) Flag ...
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The following procedure should be used to exchange data in Multi-Processor Communi- cation mode: 1. All Slave ...
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When the TXCIE bit in UCR is set, setting of TXC causes the UART Transmit Complete interrupt to be executed. TXC is cleared by hardware when executing the corresponding interrupt handling vector. Alternatively, the TXC bit is cleared (zero) by ...
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UART Control and Status Register B – UCSRB • Bit 7 – RXCIE: RX Complete Interrupt Enable When this bit is set (one), a setting of the RXC bit in USR will cause the Receive Com- plete interrupt routine to ...
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For standard crystal frequencies, the most commonly used baud rates can be generated by using the UBR settings in Table 27. UBR values which yield an actual baud rate dif- fering less than 2% from the target baud rate, ...
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UART Baud Rate Registers – UBRR and UBRRHI This is a 12-bit register which contains the UART Baud Rate according to the equation on the previous page. The UBRRHI contains the four most significant bits, and the UBRR contains the ...
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Table 28. UBR Settings at Various Crystal Frequencies in ...
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Two-wire Serial The Two-wire Serial Interface supports bi-directional serial communication designed primarily for simple but efficient integrated circuit (IC) control. The system is Interface (Byte comprised of two lines, SCL (Serial Clock) and SDA (Serial Data) that carry ...
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Figure 51. Block Diagram of the Two-wire Serial Interface The CPU interfaces with the Two-wire Serial Interface via the following five I/O Regis- ters: the Two-wire Serial Interface Bit Rate Register (TWBR), the Two-wire Serial Interface Control Register (TWCR), the ...
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The Two-wire Serial Interface Bit Rate Register – TWBR • Bits 7..0 – Two-wire Serial Interface Bit Rate Register TWBR selects the division factor for the bit rate generator. The bit rate generator is a frequency divider which generates the ...
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Bit 6 – TWEA: Two-wire Serial Interface Enable Acknowledge Flag TWEA Flag controls the generation of the acknowledge pulse. If the TWEA bit is set, the ACK pulse is generated on the Two-wire Serial Bus if the following conditions ...
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Bit 0 – TWIE: Two-wire Serial Interface Interrupt Enable When this bit is enabled, and the I-bit in SREG is set, the Two-wire Serial Interface inter- rupt will be activated for as long as the TWINT Flag is high. ...
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The Two-wire Serial Interface (Slave) Address Register – TWAR • Bits 7..1 – TWA: Two-wire Serial Interface (Slave) Address Register These seven bits constitute the slave address of the Two-wire Serial Bus unit. • Bit 0 – TWGCE: Two-wire Serial ...
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When the Two-wire Serial Interface Interrupt Flag is set, the status code in TWSR is used to determine the appropriate software action. For each status code, the required software action and details of the following serial transfer are given in ...
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After a repeated START condition (state $10), the Two-wire Serial Interface may switch to the Master Transmitter mode by loading TWDR with SLA+W or access a new Slave as Master Receiver or Transmitter. Assembly code illustrating operation of the Master ...
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Slave Transmitter Mode In the Slave Transmitter mode, a number of data bytes are transmitted to a Master Receiver (see Figure 55). The transfer is initialized as in the Slave Receiver mode. When TWAR and TWCR have been initialized, the ...
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Table 32. Status Codes for Master Transmitter Mode Status of the Two-wire Serial Status Code Bus and Two-wire Serial Inter- (TWSR) face Hardware $08 A START condition has been transmitted $10 A repeated START condition has been transmitted $18 SLA+W ...
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Figure 52. Formats and States in the Master Transmitter Mode Assembly Code Example – Master Transmitter Mode ATmega163( Successfull S SLA W A Transmission to a Slave Receiver $08 $18 Next Transfer Started with a Repeated Start Condition ...
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ERROR ldi r16, 0xc8 ; Load SLA+W into TWDR Register out TWDR, r16 ldi r16, (1<<TWINT) | (1<<TWEN) out TWCR, r16 ; Clear TWINT bit in TWCR to start transmission of address wait2:in r16, TWCR ; Wait for ...
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Table 33. Status Codes for Master Receiver Mode Status of the Two-wire Serial Status Code Bus and Two-wire Serial Inter- (TWSR) face hardware $08 A START condition has been transmitted $10 A repeated START condition has been transmitted $38 Arbitration ...
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Assembly Code Example – Master Receiver Mode 1142E–AVR–02/03 ;Part specific include file and TWI include file must be included. ; <Initialize registers TWAR and TWBR> ldi r16, (1<<TWINT) | (1<<TWSTA) | (1<<TWEN) out TWCR, r16 ;Send START condition wait5:in r16,TWCR ...
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ATmega163(L) 94 sbrs r16, TWINT ; data has been received and ACK returned rjmp wait8 in r16, TWSR ; Check value of TWI Status Register. If status cpi r16, MR_DATA_ACK ; different from MR_DATA_ACK ERROR brne ERROR in ...
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Table 34. Status Codes for Slave Receiver Mode Status of the Two-wire Serial Bus Status code and Two-wire Serial Interface (TWSR) hardware $60 Own SLA+W has been received; ACK has been returned $68 Arbitration lost in SLA+R/W as master; own ...
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Figure 54. Formats and States in the Slave Receiver Mode Assembly Code Example – Slave Receiver Mode ATmega163(L) 96 Reception of the Own S SLA W Slave Address and One or More Data Bytes. All are Acknowledged Last Data Byte ...
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ACK should be returned after receiving first ; data byte wait12:in r16,TWCR ; Wait for TWINT flag set. This indicates that sbrs r16, TWINT ; data has been received and ACK returned rjmp wait12 in r16, TWSR ; ...
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Table 35. Status Codes for Slave Transmitter Mode Status of the Two-wire Serial Bus Status Code and Two-wire Serial Interface (TWSR) hardware $A8 Own SLA+R has been received; ACK has been returned $B0 Arbitration lost in SLA+R/W as master; own ...
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Assembly Code Example – Slave Transmitter Mode 1142E–AVR–02/03 ; Part specific include file and TWI include file must be included. ; <Initialize registers, including TWAR, TWBR and TWCR> ldi r16, (1<<TWINT) | (1<<TWEA) | (1<<TWEN) out TWCR, r16 Transmitter Mode ...
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Table 36. Status Codes for Miscellaneous States Status Code Status of the Two-wire Serial (TWSR) Bus and Two-wire Serial Inter- face hardware $F8 No relevant state information available; TWINT = “0” $00 Bus error due to an illegal START or ...
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ST_DATA_NACK =$C0 ;Data byte has been tramsmitted and NACK ;received .equ ST_LAST_DATA =$C8 ;Last byte in I2DR has been transmitted (TWEA = ;’0’), ACK has been received ;***** Slave Receiver staus codes ***** .equ SR_SLA_ACK =$60 ;SLA+R has ...
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The Analog The Analog Comparator compares the input values on the positive pin PB2 (AIN0) and negative pin PB3 (AIN1). When the voltage on the positive pin PB2 (AIN0) is higher than Comparator the voltage on the negative pin PB3 ...
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Bit 5 – ACO: Analog Comparator Output ACO is directly connected to the comparator output. • Bit 4 – ACI: Analog Comparator Interrupt Flag This bit is set (one) when a comparator output event triggers the Interrupt mode defined ...
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Analog Comparator It is possible to select any of the PA7..0 (ADC7..0) pins to replace the negative input to the Analog Comparator. The ADC multiplexer is used to select this input, and conse- Multiplexed Input quently, the ADC must be ...
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Analog to Digital Converter Feature List • • • • • • • • • • • • • The ATmega163 features a 10-bit successive approximation ADC. The ADC is con- nected to an 8-channel Analog Multiplexer which allows each ...
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Figure 57. Analog to Digital Converter Block Schematic Operation The ADC converts an analog input voltage to a 10-bit digital value through successive approximation. The minimum value represents AGND and the maximum value repre- sents the voltage on the AREF ...
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ADEN is cleared recommended to switch off the ADC before entering power saving sleep modes. A conversion is started by writing a logical one to the ADC Start Conversion bit, ADSC. This bit stays ...
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When initiating a conversion by setting the ADSC bit in ADCSR, the conversion starts at the following rising edge of the ADC clock cycle. A normal conversion takes 13 ADC clock cycles. In certain situations, the ADC needs more clock ...
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Figure 61. ADC Timing Diagram, Free Run Conversion Table 39. ADC Conversion Time ADC Noise Canceler The ADC features a Noise Canceler that enables conversion during ADC Noise Reduc- tion mode (see “Sleep Modes” on page 35) to reduce noise ...
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The ADC Multiplexer Selection Register – ADMUX • Bit 7, 6 – REFS1..0: Reference Selection Bits These bits select the voltage reference for the ADC, as shown in Table 17. If these bits are changed during a conversion, the change ...
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Table 41. Input Channel Selections (Continued) The ADC Control and Status Register – ADCSR • Bit 7 – ADEN: ADC Enable Writing a logical “1” to this bit enables the ADC. By clearing this bit to zero, the ADC is ...
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Bits 2..0 – ADPS2..0: ADC Prescaler Select Bits These bits determine the division factor between the XTAL frequency and the input clock to the ADC. Table 42. ADC Prescaler Selections The ADC Data Register – ADCL and ADCH ADLAR ...
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Scanning Multiple Since change of analog channel always is delayed until a conversion is finished, the Free Running mode can be used to scan multiple channels without interrupting the con- Channels verter. Typically, the ADC Conversion Complete interrupt will be ...
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ADC Characteristics Table 43. ADC Characteristics Symbol Parameter Resolution Absolute accuracy Absolute accuracy Absolute accuracy Integral Non-linearity Differential Non-linearity Zero Error (Offset) Conversion Time Clock Frequency AV Analog Supply Voltage CC V Reference Voltage REF VINT Internal Voltage Reference V ...
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I/O Ports All AVR ports have true Read-Modify-Write functionality when used as general digital I/O ports. This means that the direction of one port pin can be changed without uninten- tionally changing the direction of any other pin with the ...
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PUD bit has to be set. The Port A pins are tri-stated when a reset condition becomes active, even if the clock is not running. Table 44. DDAn Effects on PORTA Pins Note: PORT A Schematics Note that all port ...
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Port B Port 8-bit bi-directional I/O port with internal pull-ups. Three I/O memory address locations are allocated for Port B, one each for the Data Register – PORTB, $18($38), Data Direction Register – DDRB, $17($37) and the ...
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Port B As General Digital I/O All eight bits in Port B are equal when used as digital I/O pins. PBn, General I/O pin: The DDBn bit in the DDRB Register selects the direction of this pin, if DDBn is ...
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AIN1 – PORTB, Bit 3 AIN1, Analog Comparator Negative input. When configured as an input (DDB3 is cleared (zero)) and with the internal MOS pull up resistor switched off (PB3 is cleared (zero)), this pin also serves as the ...
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Figure 65. PORTB Schematic Diagram (Pins PB2 and PB3) Figure 66. PORTB Schematic Diagram (Pin PB4) ATmega163(L) 120 MOS PUD PULL- UP PBn RL PWRDN RP WP: WRITE PORTB WD: WRITE DDRB RL: READ PORTB LATCH RP: READ PORTB PIN ...
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Figure 67. PORTB Schematic Diagram (Pin PB5) Figure 68. PORTB Schematic Diagram (Pin PB6) 1142E–AVR–02/03 MOS PUD PULL- UP PB5 WP: WRITE PORTB WD: WRITE DDRB RL: READ PORTB LATCH RP: READ PORTB PIN RD: READ DDRB SPE: SPI ENABLE ...
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Figure 69. PORTB Schematic Diagram (Pin PB7) ATmega163(L) 122 MOS PUD PULL- UP PB7 WP: WRITE PORTB WD: WRITE DDRB RL: READ PORTB LATCH RP: READ PORTB PIN RD: READ DDRB SPE: SPI ENABLE MSTR MASTER SELECT PUD: PULL-UP DISABLE ...
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Port C Port 8-bit bi-directional I/O port with internal pull-ups. Three I/O memory address locations are allocated for the Port C, one each for the Data Register – PORTC, $15($35), Data Direction Register – DDRC, $14($34) and ...
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Table 48. DDCn Effects on PORT C Pins Note: Alternate Functions of PORTC • TOSC2 – PORTC, Bit 7 TOSC2, Timer Oscillator pin 2: When the AS2 bit in ASSR is set (one) to enable asyn- chronous clocking of Timer/Counter2, ...
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Port C Schematics Note that all port pins are synchronized. The synchronization latches are not shown in the figure. Figure 70. PORTC Schematic Diagram (Pins PC0 - PC1) 1142E–AVR–02/03 0 PUD 1 PCn 0 1 PUD: PULL-UP DISABLE n = ...
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Figure 71. PORTC Schematic Diagram (Pins PC2 - PC5) Figure 72. PORTC Schematic Diagram (Pins PC6) ATmega163(L) 126 MOS PUD PULL- UP PCn RL RP WP: WRITE PORTC WD: WRITE DDRC RL: READ PORTC LATCH RP: READ PORTC PIN RD: ...
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Figure 73. PORTC Schematic Diagram (Pins PC7) 1142E–AVR–02/03 PUD 0 1 PUD: PULL-UP DISABLE ATmega163(L) 127 ...
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Port D Port bit bi-directional I/O port with internal pull-up resistors. Three I/O memory address locations are allocated for Port D, one each for the Data Register – PORTD, $12($32), Data Direction Register – DDRD, $11($31) ...
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Port D as General Digital I/O PDn, General I/O pin: The DDDn bit in the DDRD Register selects the direction of this pin. If DDDn is set (one), PDn is configured as an output pin. If DDDn is cleared (zero), ...
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INT0 – PORTD, Bit 2 INT0, External Interrupt Source 0: The PD2 pin can serve as an External Interrupt Source to the MCU. See the interrupt description for further details, and how to enable the source. • TXD – ...
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Figure 75. PORTD Schematic Diagram (Pin PD1) Figure 76. PORTD Schematic Diagram (Pins PD2 and PD3) 1142E–AVR–02/03 MOS PUD PULL- UP PD1 WP: WRITE PORTD WD: WRITE DDRD RL: READ PORTD LATCH RP: READ PORTD PIN READ DDRD RD: UART ...
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Figure 77. PORTD Schematic Diagram (Pins PD4 and PD5) Figure 78. PORTD Schematic Diagram (Pin PD6) ATmega163(L) 132 PUD PUD: PULL-UP DISABLE MOS PUD PULL- UP PD6 RL RP WP: WRITE PORTD 0 NOISE CANCELER WD: WRITE DDRD 1 RL: ...
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Figure 79. PORTD Schematic Diagram (Pin PD7) 1142E–AVR–02/03 PUD PUD: PULL-UP DISABLE ATmega163(L) 133 ...
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Memory Programming Boot Loader Support The ATmega163 provides a mechanism for Programming and Re-programming code by the MCU itself. This feature allows flexible application software updates, controlled by the MCU using a Flash-resident Boot Loader program. This makes it possible ...
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Figure 80. Memory Sections 1142E–AVR–02/03 Program Memory Pages BOOTSZ = '11' Application Flash Section 126 (8064 x 16) Boot Flash Section 2 (128 x 16) Program Memory Pages BOOTSZ = '01' Application Flash Section 120 (7680 x 16) Boot Flash ...
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Entering the Boot Loader The SPM instruction can access the entire Flash, but can only be executed from the Program Boot Loader Flash section Boot Loader capability is needed, the entire Flash is available for application code. Entering ...
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Perform a Page Write To execute Page Write, set up the address in the Z-pointer, write “00101” to the five LSB in SPMCR and execute SPM within four clock cycles after writing SPMCR. The data in R1 and R0 is ...
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Table 53. Boot Lock Bit0 Protection Modes (Application Section) Note: Table 54. Boot Lock Bit1 Protection Modes (Boot Loader Section) Note: Setting the Boot Loader Lock To set the Boot Loader Lock bits, write the desired data to R0, write ...
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The algorithm for reading the Fuse Low bits is similar to the one described above for reading the Lock bits. To read the Fuse Low bits, load the Z-pointer with $0000 and set the BLBSET and SPMEN bits in SPMCR. ...
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Store Program Memory The Store Program Memory Control Register contains the control bits needed to control Control Register – SPMCR the programming of the Flash from internal code execution. • Bit 7 – Res: Reserved Bit This bit is a ...
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Bit 0 – SPMEN: Store Program Memory Enable This bit enables the SPM instruction for the next four clock cycles. If set together with either ASRE, BLBSET, PGWRT, or PGERS, the following SPM instruction will have a special meaning, ...
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ATmega163(L) 142 ; re-enable the Application Section ldi spmcrval, (1<<ASRE) + (1<<SPMEN) call Do_spm ; transfer data from RAM to Flash page buffer ldi looplo, low(PAGESIZEB) ldi loophi, high(PAGESIZEB) Wrloop r1, Y+ ldi spmcrval, (1<<SPMEN) call ...
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Program and Data The ATmega163 provides six Lock bits which can be left unprogrammed (“1”) or can be programmed (“0”) to obtain the additional features listed in Table 55. The Lock bits can Memory Lock Bits only be erased to ...
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... Lock bit1 (LB1) is programmed. Program the Fuse bits before programming the Lock bits. Signature Bytes All Atmel microcontrollers have a three-byte signature code which identifies the device. This code can be read in both serial and parallel mode. The three bytes reside in a sep- arate address space. ...
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Parallel Programming This section describes how to Parallel Program and verify Flash Program memory, EEPROM Data memory + Program And Data Memory Lock bits and Fuse bits in the ATmega163. Pulses are assumed least 500ns unless otherwise ...
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Table 56. Pin Name Mapping (Continued) Table 57. XA1 and XA0 Coding Table 58. Command Byte Bit Coding Enter Programming Mode The following algorithm puts the device in Parallel Programming mode: 1. Apply 4.5 - 5.5V between V 2. Set ...
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Set DATA to “1000 0000”. This is the command for Chip Erase. 4. Give WR a negative pulse. This starts the Chip Erase. RDY/BSY goes low. 5. Wait until RDY/BSY goes high before loading a new command. Programming the ...
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H. Load Address High byte I. Program Page J. End Page Programming K. Repeat A through J 128 times or until all data has been programmed. Figure 82. Programming the Flash Waveforms DY/BSY RESET PAGEL ATmega163(L) 148 1. 1. Set ...
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Figure 83. Programming the Flash Waveforms (continued) Programming the EEPROM The programming algorithm for the EEPROM Data Memory is as follows (refer to “Pro- gramming the Flash” on page 147 for details on Command, Address and Data loading ...
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Figure 84. Programming the EEPROM Waveforms Reading the Flash The algorithm for reading the Flash memory is as follows (refer to “Programming the Flash” on page 147 for details on Command and Address loading Load Command “0000 0010”. ...
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Programming the Fuse High The algorithm for programming the Fuse high bits is as follows (refer to “Programming Bits the Flash” on page 147 for details on Command and Data loading Load Command “0100 0000” Load ...
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Reading the Signature Bytes The algorithm for reading the Signature bytes is as follows (refer to Programming the Flash for details on Command and Address loading Load Command “0000 1000” Load Address Low Byte ($00 - ...
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Parallel Programming Figure 85. Parallel Programming Timing Characteristics Table 59. Parallel Programming Characteristics, T Notes: 1142E–AVR–02/ XTAL1 XHXL t t DVXH Data & Contol (DATA, XA0/1, BS1, BS2 BVPH PAGEL t PHPL WR t RDY/BSY OE ...
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Serial Downloading Both the Flash and EEPROM memory arrays can be programmed using the serial SPI bus while RESET is pulled to GND. The serial interface consists of pins SCK, MOSI (input) and MISO (output). After RESET is set low, ...
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Serial Programming When writing serial data to the ATmega163, data is clocked on the rising edge of SCK. Algorithm When reading data from the ATmega163, data is clocked on the falling edge of SCK. See Figure 87, Figure 88 and ...
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Data Polling Flash When a page is being programmed into the Flash, reading an address location within the page being programmed will give the value $FF. At the time the device is ready for a new page, the programmed value ...
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Figure 87. Serial Programming Waveforms 1142E–AVR–02/03 SERIAL DATA INPUT MSB PB5 (MOSI) SERIAL DATA OUTPUT MSB PB6 (MISO) SERIAL CLOCK INPUT PB7(SCK) SAMPLE ATmega163(L) LSB LSB 157 ...
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Table 61. Serial Programming Instruction Set Instruction Byte 1 Programming Enable 1010 1100 Chip Erase 1010 1100 Read Program Memory 0010 H000 Load Program Memory Page 0100 H000 Write Program Memory Page 0100 1100 Read EEPROM Memory 1010 0000 ...
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Serial Programming Figure 88. Serial Programming Timing Characteristics Table 62. Serial Programming Characteristics, T (Unless otherwise noted) 1142E–AVR–02/03 MOSI t OVSH SCK MISO Symbol Parameter 1/t Oscillator Frequency (V = 2.7 - 5.5 V) CLCL CC t Oscillator Period (V ...
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Electrical Characteristics Absolute Maximum Ratings* Operating Temperature ................................. - +125 C Storage Temperature .................................... -65°C to +150°C Voltage on any Pin except RESET with respect to Ground ................................-1. Voltage on RESET with respect to Ground .....-1.0V ...
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... If IOH exceeds the test condition, V greater than the listed test condition. 5. Minimum V for Power-down is 2.5V. CC External Clock Drive Figure 89. External Clock Drive Waveforms Waveforms 1142E–AVR–02/03 Condition Min Active 4 MHz (ATmega163L) Active 8 MHz (ATmega163) Idle 4 MHz (ATmega163L) Idle 8 MHz (ATmega163) WDT enabled WDT disabled ...
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External Clock Drive Table 63. External Clock Drive Table 64. External RC Oscillator, typical frequencies Note: ATmega163(L) 162 Symbol Parameter 1/t Oscillator Frequency CLCL t Clock Period CLCL t High Time CHCX t Low Time CLCX t Rise Time CLCH ...
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Two-wire Serial Interface Characteristics Table 65 describes the requirements for devices connected to the Two-wire Serial Bus. The ATmega163 Two-wire Serial Interface meets or exceeds these requirements under the noted conditions. Timing symbols refer to Figure 90. Table 65. Two-wire ...
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Figure 90. Two-wire Serial Bus Timing SCL t t SU;STA HD;STA SDA ATmega163(L) 164 t HIGH LOW LOW t HD;DAT t t SU;DAT 1142E–AVR–02/03 SU;STO t BUF ...
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Typical The following charts show typical behavior. These figures are not tested during manu- facturing. All current consumption measurements are performed with all I/O pins Characteristics configured as inputs and with internal pull-ups enabled. All pins on Port F are ...
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Figure 92. Analog Comparator Offset Voltage vs. Common Mode Voltage (V Figure 93. Analog Comparator Input Leakage Current (V ATmega163(L) 166 0.5 1 Common Mode Voltage ( ...
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Figure 94. Watchdog Oscillator Frequency vs. V Sink and source capabilities of I/O ports are measured on one pin at a time. Figure 95. Pull-up Resistor Current vs. Input Voltage (V 1142E–AVR–02/03 1600 1400 1200 1000 800 600 400 200 ...
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Figure 96. Pull-up Resistor Current vs. Input Voltage (V Figure 97. I/O Pin Sink Current vs. Output Voltage (V ATmega163(L) 168 ˚ ˚ ...
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Figure 98. I/O Pin Source Current vs. Output Voltage (V Figure 99. I/O Pin Sink Current vs. Output Voltage (V 1142E–AVR–02/ ˚ ˚ ...
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Figure 100. I/O Pin Source Current vs. Output Voltage (V Figure 101. I/O Pin Input Threshold vs. V ATmega163(L) 170 ˚ ˚ ...
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Figure 102. I/O Pin Input Hysteresis vs. V 1142E–AVR–02/03 0.18 0.16 0.14 0.12 0.1 0.08 0.06 0.04 0.02 0 2.7 4.0 ATmega163( 5 171 ...
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Register Summary Address Name Bit 7 $3F ($5F) SREG I $3E ($5E) SPH – $3D ($5D) SPL SP7 $3C ($5C) Reserved $3B ($5B) GIMSK INT1 $3A ($5A) GIFR INTF1 $39 ($59) TIMSK OCIE2 $38 ($58) TIFR OCF2 $37 ($57) SPMCR ...
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Register Summary (Continued) Address Name Bit 7 $00 ($20) TWBR Two-wire Serial Interface Bit Rate Register Note: 1. For compatibility with future devices, reserved bits should be written to zero if accessed. Reserved I/O memory addresses should never be written. ...
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Instruction Set Summary Mnemonics Operands Description ARITHMETIC AND LOGIC INSTRUCTIONS ADD Rd, Rr Add two Registers ADC Rd, Rr Add with Carry two Registers ADIW Rdl,K Add Immediate to Word SUB Rd, Rr Subtract two Registers SUBI Rd, K Subtract ...
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Instruction Set Summary (Continued) BRIE k Branch if Interrupt Enabled BRID k Branch if Interrupt Disabled DATA TRANSFER INSTRUCTIONS MOV Rd, Rr Move Between Registers MOVW Rd, Rr Copy Register Word LDI Rd, K Load Immediate LD Rd, X Load ...
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Instruction Set Summary (Continued) CLH Clear Half Carry Flag in SREG NOP No Operation SLEEP Sleep WDR Watchdog Reset ATmega163(L) 176 None (see specific descr. for Sleep function) None (see specific descr. for WDR/timer) None 1 1 ...
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... Thin (1.0 mm) Plastic Gull Wing Quad Flat Package (TQFP) 40P6 40-lead, 0.600" Wide, Plastic Dual Inline Package (PDIP) 1142E–AVR–02/03 Ordering Code Package ATmega163L-4AC 44A ATmega163L-4PC 40P6 ATmega163L-4AI 44A ATmega163L-4PI 40P6 ATmega163-8AC 44A ATmega163-8PC ...
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Packaging Information 44A PIN 0˚~7˚ Notes: 1. This package conforms to JEDEC reference MS-026, Variation ACB. 2. Dimensions D1 and E1 do not include mold protrusion. Allowable protrusion is 0.25 mm per side. Dimensions D1 and E1 ...
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A SEATING PLANE Notes: 1. This package conforms to JEDEC reference MS-011, Variation AC. 2. Dimensions D and E1 do not include mold Flash or Protrusion. Mold Flash or Protrusion shall not exceed 0.25 mm (0.010"). ...
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Erratas ATmega163(L) Errata • • Rev. F • • • • 6. Increased Interrupt Latency 5. Interrupts Abort TWI Power-down 4. TWI Master Does not Accept Spikes on Bus Lines 3. TWCR Write Operation Ignored ATmega163(L) 180 Increased Interrupt Latency ...
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PWM not Phase Correct 1. TWI is Speed Limited in Slave Mode 1142E–AVR–02/03 Problem Fix/Workaround Ensure at least one instruction (e.g., nop) is executed between two writes to TWCR. In Phase-correct PWM mode, a change from OCRx = TOP ...
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Change Log This section containes a log on the changes made to the data sheet for ATmega163. All refereces to pages in Change Log, are referred to this document. Changes from Rev. 1. Added “Not Recommend for New Designs. Use ...
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Table of Contents Features................................................................................................. 1 Pin Configurations................................................................................ 2 Description ............................................................................................ 3 Block Diagram....................................................................................... 3 Architectural Overview......................................................................... 7 Timer/Counters ................................................................................... 39 Watchdog Timer.................................................................................. 60 EEPROM Read/Write Access............................................................. 62 Serial Peripheral Interface – SPI........................................................ 65 UART.................................................................................................... 70 1142E–AVR–02/03 Pin Descriptions.................................................................................................... 4 Clock ...
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Two-wire Serial Interface (Byte Oriented) ........................................ 80 The Analog Comparator................................................................... 102 Analog to Digital Converter ............................................................. 105 I/O Ports............................................................................................. 115 Memory Programming...................................................................... 134 Electrical Characteristics................................................................. 160 External Clock Drive Waveforms .................................................... 161 External Clock Drive......................................................................... 162 ATmega163(L) ii Two-wire Serial ...
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Two-wire Serial Interface Characteristics ...................................... 163 Typical Characteristics .................................................................... 165 Register Summary ............................................................................ 172 Instruction Set Summary ................................................................. 174 Ordering Information........................................................................ 177 Packaging Information ..................................................................... 178 Erratas ............................................................................................... 180 Change Log ....................................................................................... 182 Table of Contents .................................................................................. i 1142E–AVR–02/03 44A ...
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ATmega163(L) iv 1142E–AVR–02/03 ...
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... No licenses to patents or other intellectual property of Atmel are granted by the Company in connection with the sale of Atmel products, expressly or by implication. Atmel’s products are not authorized for use as critical components in life support devices or systems. ...